- 21 May, 2021 1 commit
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Igor Opaniuk authored
In iMX8MM it is possible to have two copies of bootloader in SD/eMMC and switch between them. The switch is triggered either by the BootROM in case the bootloader image is faulty OR can be enforced by the user. To trigger that switch the PERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register. As the bit is retained after WARM reset, that permits to control BootROM behavior regarding what boot image it will boot after reset: primary or secondary. This is useful for reliable bootloader A/B updates, as it permits switching between two copies of bootloader at different offsets of the same storage. If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads that secondary image table from address 0x8200 on the boot media and uses the address specified in the table for the secondary image. Secondary Image Table contains the sector of secondary bootloader image, exluding the offset to that image (explained below in the note). To generate the Secondary Image Table, use e.g.: $ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11' '\x00\x00\x10\x0\x0\x00\x0\x0\x0' > /tmp/sit.bin $ hexdump -vC /tmp/sit.bin 00000000 00 00 00 00 00000004 00 00 00 00 00000008 33 22 11 00 <--- This is the "tag" 0000000c 00 10 00 00 <--- This is the "firstSectorNumber" 00000010 00 00 00 00 You can also use NXP script from [1][2] imx-mkimage tool for SIT generation. Note that the firstSectorNumber is NOT the offset of the IVT, but an offset of the IVT decremented by Image Vector Table offset (Table 6-25. Image Vector Table Offset and Initial Load Region Size for iMX8MM/MQ), so for secondary SPL copy at offset 0x1042 sectors, firstSectorNumber must be 0x1000 (0x42 sectors * 512 = 0x8400 bytes offset). In order to test redundant boot board should be closed and SD/MMC manufacture mode disabled, as secondary boot is not supported in the SD/MMC manufacture mode, which can be disabled by blowing DISABLE_SDMMC_MFG (example for iMX8MM): > fuse prog -y 2 1 0x00800000 For additional details check i.MX 8M Mini Apllication Processor Reference Manual, 6.1.5.4.5 Redundant boot support for expansion device chapter. [1] https://source.codeaurora.org/external/imx/imx-mkimage/ [2] scripts/gen_sit.sh Change-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
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- 23 Mar, 2021 2 commits
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Ying-Chun Liu (PaulLiu) authored
Adds a number of definitions consistent with the established WaRP7 equivalents specifying number of io_handles and block devices. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3
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Ying-Chun Liu (PaulLiu) authored
Allows for exporting of FIP related methods cleanly in a private header. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c
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- 19 Aug, 2020 1 commit
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Jacky Bai authored
The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
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- 06 Aug, 2020 1 commit
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Peng Fan authored
Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor could use SDEI to do hypervisor management, after physical IRQ has been disabled routing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5fd697fee22df151e13d0f1335e8ac8a7bae6189
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- 10 Jul, 2020 1 commit
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Jacky Bai authored
Although the GPC provides the similar functions for all the i.MX8M SoC family, the HW register offset and bit defines still have some slight difference, so move the hw reg offset & most of the bitfield defines in 'gpc_reg.h' that is specific to each SoC. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f
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- 05 Mar, 2020 1 commit
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Igor Opaniuk authored
Some boards (f.e. Verdin i.MX8M Mini) use different UART base address for serial debug output, so make this value configurable (as a build option). Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004
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- 05 Nov, 2019 1 commit
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Jacky Bai authored
Add the basic support for opteed SPD on imx8mq & imx8mm. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce
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- 04 Jul, 2019 1 commit
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Jacky Bai authored
CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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- 13 Mar, 2019 1 commit
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Jacky Bai authored
The i.MX8M Mini is new SOC of the i.MX8M family. it is focused on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. The i.MX 8M Mini Media Applications Processor is 14nm FinFET product of the growing i.MX8M family targeting the consumer & industrial market. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad Cortex-A53 cluster with video and graphics accelerators this patch add the basic support for i.MX8MM. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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