GitLab

Commit fdb1964c

 ("xlat: Introduce
MAP_REGION2() macro") added a granularity field to mmap_region_t.

Tegra platforms were using the v2 xlat_tables implementation in
common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c
where arrays are being defined. This caused the next physical address to
be read as granularity, causing EINVAL error and triggering an assert.

Consistently use xlat_tables_v2.h header to avoid this.

Fixes ARM-software/tf-issues#548.
Signed-off-by: Andreas Färber <afaerber@suse.de>

ARM platforms: Fix console address for flush

Remove URLs from comments

optee: print header info before validate

This fixes all defects according to MISRA Rule 3.1: "The character
sequences /* and // shall not be used within a comment". This affects
all URLs in comments, so they have been removed:

- The link in `sdei_state.c` can also be found in the documentation file
  `docs/sdei.rst`.

- The bug that the file `io_fip.c` talks about doesn't affect the
  currently supported version of GCC, so it doesn't make sense to keep
  the comment. Note that the version of GCC officially supported is the
  one that comes with Linaro Release 17.10, which is GCC 6.2.

- The link in `tzc400.c` was broken, and it didn't correctly direct to
  the Technical Reference Manual it should. The link has been replaced
  by the title of the document, which is more convenient when looking
  for the document.

Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

The console core flush API expects the base address in the first
register, but ARM helpers currently sets the second register with the
base address. This causes an assert failure.

This patch fixes that.

Change-Id: Ic54c423cd60f2756902ab3cfc77b3de2ac45481e
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

TSP changes for EHF

maintainers.rst: Add maintainer for plat Poplar

poplar: misc updates

zlib: Fix build error when LOG_LEVEL=50

When enabling VERBOSE() traces, the zlib library fails to compile
because of an incompatible format specifier string. Fix that.

Change-Id: I74ff1c8dc2e6157ee982f7754bce4504599e3013
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Fix zero_normalmem() for BL2_AT_EL3

Currently optee header info is only printed after it is validated,
but this does not help with debugging in case of error, so print it
before.
Signed-off-by: Victor Chong <victor.chong@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Signed-off-by: Victor Chong <victor.chong@linaro.org>

support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu

As per MISRA C-2012 Rule 10.4.
arg0 is a u_register_t, can be a 32bit or 64bit upon architecture.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

Change-Id: Id2e2800af59ca35fc0c4cfdddd9f5c5afd56a4db
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:

  1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received
     at the TSP's exception vector, and TSP voluntarily preempts itself.

  2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a
     trap to EL3, which preempts TSP execution.

When EL3 exception handling is in place (i.e.,
EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system
with GICv3, pending NS interrupts while TSP is executing will be
signalled as FIQ (which traps to EL3). This situation necessitates the
same treatment applied to case (2) above.

Therefore, when EL3 exception handling is in place, additionally
require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1.

Strictly speaking, this is not required on a system with GICv2, but the
same model is uniformly followed regardless, for simplicity.

Relevant documentation updated.

Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

When EL3 exception handling is in effect (i.e.,
EL3_EXCEPTION_HANDLING=1), Non-secure interrupts can't preempt Secure
execution. However, for yielding SMCs, preemption by Non-secure
interupts is intended.

This patch therefore adds a call to ehf_allow_ns_preemption() before
dispatching a Yielding SMC to TSP.

Change-Id: Ia3a1ae252f3adc0f14e6d7e0502f251bdb349bdf
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1,
EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-secure and
secure execution.

The interrupt management framework currently treats EL3 interrupt
routing as valid. For the above reason, this patch makes them invalid
when EL3_EXCEPTION_HANDLING is in effect.

Change-Id: I95bca8f5dc8df8eb0ff6f305cfba098611522a39
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Commit 21b818c0

 (BL31: Introduce
Exception Handling Framework) introduced the build option
EL3_EXCEPTION_HANDLING, but missed to pass that to the build command
line. This patch fixes that.

Change-Id: I0a1be2c7b41a81e748ad7d6cf795aab7f6d19193
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Support GZIP-compressed images for faster loading and verification

Define Qemu AArch32 implementation for some platform functions
(core position, secondary boot cores, crash console). These are
derived from the AArch64 implementation.

BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is
the first executable image after BL2.

Support SP_MIN and OP-TEE as BL32: create a sp_min make script target
in Qemu, define mapping for IMAGE_BL32

Minor fix Qemu return value type for plat_get_ns_image_entrypoint().

Qemu model for the Cortex-A15 does not support the virtualization
extension although the core expects it. To overcome the issue, Qemu
ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0.

Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform
used by the Qemu platform.

Qemu Cortex-A15 model integrates a single cluster with up to 4 cores.

Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

AArch32 only platforms can boot the OP-TEE secure firmware as
a BL32 secure payload. Such configuration can be defined through
AARCH32_SP=optee.

The source files can rely on AARCH32_SP_OPTEE to condition
OP-TEE boot specific instruction sequences.

OP-TEE does not expect ARM Trusted Firmware formatted structure
as boot argument. Load sequence is expected to have already loaded
to OP-TEE boot arguments into the bl32 entrypoint info structure.

Last, AArch32 platform can only boot AArch32 OP-TEE images.

Change-Id: Ic28eec5004315fc9111051add6bb1a1d607fc815
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

uniphier: fix and improve memory layout

Add 'lr_svc' as a boot parameter in AArch32 bl1. This is used by Optee
and Trusty to get the non-secure entry point on AArch32 platforms.

This change is not ported in AArch64 mode where the BL31, not BL32,
is in charge of booting the non secure image (BL33).
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

AMUv1 support for AArch32

Looks like this is requirement in the pre-merge static analysis.

misra_violation: [Required] MISRA C-2012 Rule 7.2 violation:
Unsigned constants must be declared with U or u suffix.

Adding ULL as requested.  I used ULL() macros for BL*_{BASE,LIMIT}
because they are referenced from linker scripts.
Requested-by: David Cunado <david.cunado@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Currently, the xlat region of the on-chip SRAM is always allocated
for all BL images.

The access to the on-chip SRAM is necessary for loading images from
a USB memory device (i.e. when updating firmware), so unneeded for
the usual boot procedure.

To avoid this waste, allocate the xlat region dynamically only for
BL2, and only when it is necessary.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Commit 247fc043

 ("uniphier: switch to BL2-AT-EL3 and remove BL1
support") accidentally changed the location of BL31 and BL32.  The
new memory map overlaps with the audio DSP images, also gives impact
to OP-TEE.  They are both out of control of ARM Trusted Firmware, so
not easy to change.  This commit restores the image layout that was
originally used prior to the BL2-AT-EL3 migration.
Reported-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

rockchip/rk3399: Fix memory corruptions or illegal memory access

Analyze coding style of patches individually

Allow to handle GZIP-compressed images by giving FIP_GZIP=1 from the
command line.

- Images are GZIP-compressed, then packed into FIP.  If Trusted Board
  Boot is enabled, certificates are generated based on the compressed
  images.

- GZIP decompressor is linked into BL2 to decompress images at
  run-time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

In the next commit, I will have more usecases to get struct image_info
from image ID.  It is better to make a helper function at a different
layer.  I do not need the current uniphier_image_descs_fixup() since
the code is small enough to be squashed into the caller side.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>