- 29 Jan, 2020 1 commit
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Hadi Asyrafi authored
This patch enables uboot's spl entrypoint to BL31 and also handles secondary cpus state during cold boot. Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by:Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47
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- 16 Jan, 2020 7 commits
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Hadi Asyrafi authored
Create a function to check for fpga readiness, and move the checking out of bridge enable function. Signed-off-by: -
Hadi Asyrafi authored
This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: -
Hadi Asyrafi authored
SiP CONFIG_ISDONE now will query status for either CONFIG_STATUS or RECONFIG_STATUS based on passed parameter Signed-off-by: -
Hadi Asyrafi authored
Refactored system manager driver to be shared across both intel platform Signed-off-by: -
Hadi Asyrafi authored
Refactor reset manager into intel common platform directory as it can be shared by both Stratix 10 and Agilex. Register address and field is now referred through macros. Signed-off-by: -
Hadi Asyrafi authored
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: -
Hadi Asyrafi authored
Combine both peripheral and bridge non-secure access code into a single callable function Signed-off-by:
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- 15 Jan, 2020 2 commits
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Tien Hock, Loh authored
UEFI decompression will fail if the payload size is too large and the load address is too low. This patch moves the payload to a higher address to fix the issue Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
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Hadi Asyrafi authored
All function in socfpga_sip_svc.c should only be called locally except sip_smc_handler(). Signed-off-by:
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- 13 Jan, 2020 1 commit
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Hadi Asyrafi authored
This patch removes un-needed r/w parameter checks for qspi driver. The driver can actually access any offset and size. Signed-off-by:
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 30 Dec, 2019 3 commits
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Hadi Asyrafi authored
Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: -
Hadi Asyrafi authored
Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: -
Hadi Asyrafi authored
Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by:
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- 17 Dec, 2019 11 commits
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Hadi Asyrafi authored
Fix FPGA reconfiguration driver logic Signed-off-by: -
Hadi Asyrafi authored
Mailbox driver now handles variable response length Signed-off-by: -
Hadi Asyrafi authored
Modify mailbox config return code to improve debugging. Signed-off-by: -
Hadi Asyrafi authored
Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: -
Tien Hock, Loh authored
Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by: -
Tien Hock, Loh authored
There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: -
Hadi Asyrafi authored
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: -
Hadi Asyrafi authored
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: -
Hadi Asyrafi authored
This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: -
Hadi Asyrafi authored
Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: -
Hadi Asyrafi authored
Separate SiP related definition from mailbox header file Signed-off-by:
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- 12 Dec, 2019 1 commit
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Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by:
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- 28 Nov, 2019 5 commits
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Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 12 Sep, 2019 2 commits
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Hadi Asyrafi authored
Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: -
Hadi Asyrafi authored
Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by:
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- 19 Aug, 2019 2 commits
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Hadi Asyrafi authored
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: -
Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by:
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- 15 Aug, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by:
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
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- 13 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by:
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