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  1. 30 Jun, 2020 1 commit
  3. 25 Jun, 2020 2 commits
  5. 22 Jun, 2020 2 commits
  7. 01 Jun, 2020 1 commit
  9. 19 May, 2020 1 commit
  11. 17 Apr, 2020 1 commit
  13. 16 Apr, 2020 1 commit
  15. 12 Mar, 2020 3 commits
    • Sandrine Bailleux's avatar
      Mention COT build option in trusted-board-boot-build.rst · d935b951
      Sandrine Bailleux authored 
      Since commit 3bff910d

 ("Introduce COT
build option"), it is now possible to select a different Chain of Trust
than the TBBR-Client one.

Make a few adjustments in the documentation to reflect that. Also make
some minor improvements (fixing typos, better formatting, ...)  along
the way.

Change-Id: I3bbadc441557e1e13311b6fd053fdab6b10b1ba2
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      d935b951
    • Sandrine Bailleux's avatar
      Update cryptographic algorithms in TBBR doc · 316c5cc6
      Sandrine Bailleux authored 
      

The TBBR documentation has been written along with an early
implementation of the code. At that time, the range of supported
encryption and hash algorithms was failry limited. Since then, support
for other algorithms has been added in TF-A but the documentation has
not been updated.

Instead of listing them all, which would clutter this document while
still leaving it at risk of going stale in the future, remove specific
references to the original algorithms and point the reader at the
relevant comprehensive document for further details.

Change-Id: I29dc50bc1d53b728091a1fbaa1c3970fb999f7d5
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      316c5cc6
    • Chris Kay's avatar
      juno/sgm: Maximize space allocated to SCP_BL2 · ddc93cba
      Chris Kay authored 
      

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: default avatarChris Kay <chris.kay@arm.com>
      ddc93cba
  17. 09 Mar, 2020 1 commit
  19. 06 Mar, 2020 1 commit
  21. 02 Mar, 2020 1 commit
  23. 20 Feb, 2020 1 commit
    • Varun Wadekar's avatar
      cpus: higher performance non-cacheable load forwarding · cd0ea184
      Varun Wadekar authored 
      

The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
non-cacheable streaming enhancement. Platforms can set this bit only
if their memory system meets the requirement that cache line fill
requests from the Cortex-A57 processor are atomic.

This patch adds support to enable higher performance non-cacheable load
forwarding for such platforms. Platforms must enable this support by
setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
makefiles. This flag is disabled by default.

Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      cd0ea184
  25. 12 Feb, 2020 1 commit
  27. 06 Feb, 2020 1 commit
    • Max Shvetsov's avatar
      Adds option to read ROTPK from registers for FVP · a6ffddec
      Max Shvetsov authored 
      

Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
In case of ROT_KEY specified - generates a new hash and replaces the
original.

Note: Juno board was tested by original feature author and was not tested
for this patch since we don't have access to the private key. Juno
implementation was moved to board-specific file without changing
functionality. It is not known whether byte-swapping is still needed
for this platform.

Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
      a6ffddec
  29. 27 Jan, 2020 1 commit
  31. 29 Dec, 2019 1 commit
    • Samuel Holland's avatar
      bl31: Split into two separate memory regions · f8578e64
      Samuel Holland authored 
      

Some platforms are extremely memory constrained and must split BL31
between multiple non-contiguous areas in SRAM. Allow the NOBITS
sections (.bss, stacks, page tables, and coherent memory) to be placed
in a separate region of RAM from the loaded firmware image.

Because the NOBITS region may be at a lower address than the rest of
BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this
region, or el3_entrypoint_common would attempt to invalidate the dcache
for the entire address space. New symbols __NOBITS_{START,END}__ are
added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the
NOBITS region is invalidated separately.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37
      f8578e64
  33. 23 Dec, 2019 1 commit
  35. 27 Nov, 2019 1 commit
    • Paul Beesley's avatar
      doc: Split the User Guide into multiple files · 43f35ef5
      Paul Beesley authored 
      

The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information from. Currently, it covers
these topics and maybe a couple more:

- Requirements (hardware, tools, libs)
- Checking out the repo
- Basic build instructions
- A comprehensive list of build flags
- FIP packaging
- Building specifically for Juno
- Firmware update images
- EL3 payloads
- Preloaded BL33 boot flow
- Running on FVPs
- Running on Juno

I have separated these out into a few groups that become new
documents. Broadly speaking, build instructions for the tools,
for TF-A generally, and for specific scenarios are separated.
Content relating to specific platforms (Juno and the FVPs are
Arm-specific platforms, essentially) has been moved into the
documentation that is specific to those platforms, under
docs/plat/arm.

Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      43f35ef5
  37. 26 Nov, 2019 1 commit
  39. 11 Oct, 2019 1 commit
  41. 08 Oct, 2019 1 commit
    • Paul Beesley's avatar
      doc: Convert internal links to RST format · 34760951
      Paul Beesley authored 
      

Currently links between documents are using the format:

<path/to/><filename>.rst

This was required for services like GitHub because they render each
document in isolation - linking to another document is like linking
to any other file, just provide the full path.

However, with the new approach, the .rst files are only the raw
source for the documents. Once the documents have been rendered
the output is now in another format (HTML in our case) and so,
when linking to another document, the link must point to the
rendered version and not the .rst file.

The RST spec provides a few methods for linking between content.
The parent of this patch enabled the automatic creation of anchors
for document titles - we will use these anchors as the targets for
our links. Additional anchors can be added by hand if needed, on
section and sub-section titles, for example.

An example of this new format, for a document with the title
"Firmware Design" is :ref:`Firmware Design`.

One big advantage of this is that anchors are not dependent on
paths. We can then move documents around, even between directories,
without breaking any links between documents. Links will need to be
updated only if the title of a document changes.

Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      34760951
  43. 04 Oct, 2019 2 commits
    • laurenw-arm's avatar
      Neoverse N1 Errata Workaround 1542419 · 80942622
      laurenw-arm authored 
      

Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.

The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: default avatarLauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
      80942622
    • Soby Mathew's avatar
      Fix the CAS spinlock implementation · c97cba4e
      Soby Mathew authored 
      

Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
on a platform build option. The CAS-based implementation used to be
unconditionally selected for all ARM8.1+ platforms.

The previous CAS spinlock implementation had a bug wherein the spin_unlock()
implementation had an `sev` after `stlr` which is not sufficient. A dsb is
needed to ensure that the stlr completes prior to the sev. Having a dsb is
heavyweight and a better solution would be to use load exclusive semantics
to monitor the lock and wake up from wfe when a store happens to the lock.
The patch implements the same.

Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
Signed-off-by: default avatarOlivier Deprez <olivier.deprez@arm.com>
      c97cba4e
  45. 12 Sep, 2019 1 commit
  47. 09 Sep, 2019 1 commit
  49. 02 Jul, 2019 9 commits
  51. 22 Jun, 2019 1 commit
  53. 06 Jun, 2019 1 commit