Skip to content

GitLab

Switch branch/tag
  1. 27 Apr, 2021 1 commit
    • Manish V Badarkhe's avatar
      fix(driver/auth): avoid NV counter upgrade without certificate validation · a2a5a945
      Manish V Badarkhe authored 
      

Platform NV counter get updated (if cert NV counter > plat NV counter)
before authenticating the certificate if the platform specifies NV
counter method before signature authentication in its CoT, and this
provides an opportunity for a tempered certificate to upgrade the
platform NV counter. This is theoretical issue, as in practice none
of the standard CoT (TBBR, dualroot) or upstream platforms ones (NXP)
exercised this issue.

To fix this issue, modified the auth_nvctr method to do only NV
counter check, and flags if the NV counter upgrade is needed or not.
Then ensured that the platform NV counter gets upgraded with the NV
counter value from the certificate only after that certificate gets
authenticated.

This change is verified manually by modifying the CoT that specifies
certificate with:
1. NV counter authentication before signature authentication
   method
2. NV counter authentication method only

Change-Id: I1ad17f1a911fb1035a1a60976cc26b2965b05166
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      a2a5a945
  3. 20 Apr, 2021 26 commits
  5. 08 Apr, 2021 2 commits
  7. 06 Apr, 2021 3 commits
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization · 40d08192
      Pali Rohár authored 
      

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
      40d08192
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call · ccec1bd5
      Pali Rohár authored 
      

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
  new_val = (old_val & ~mask) | (data & mask);
it does
  new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
 since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
      ccec1bd5
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Fix configuring polarity invert bits · ee4c70eb
      Pali Rohár authored 
      

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
      ee4c70eb
  9. 01 Apr, 2021 1 commit
  11. 26 Mar, 2021 1 commit
    • Bharat Gooty's avatar
      driver: brcm: add i2c driver · 48c6a6b6
      Bharat Gooty authored 
      

Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data

This driver is verified by reading the DDR SPD data.
Signed-off-by: default avatarBharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
      48c6a6b6
  13. 24 Mar, 2021 6 commits