- 17 Dec, 2019 4 commits
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Sandrine Bailleux authored
* changes: allwinner: Convert AXP803 regulator setup code into a driver allwinner: a64: power: Use fdt_for_each_subnode allwinner: a64: power: Remove obsolete register check allwinner: a64: power: Remove duplicate DT check allwinner: Build PMIC bus drivers only in BL31 allwinner: a64: power: Make sunxi_turn_off_soc static allwinner: Merge duplicate code in sunxi_power_down allwinner: Clean up PMIC-related error handling allwinner: Synchronize PMIC enumerations allwinner: Enable clock before resetting I2C/RSB
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Olivier Deprez authored
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Sandrine Bailleux authored
Sphinx was showing the following warning message: docs/getting_started/build-options.rst:200: WARNING: Bullet list ends without a blank line; unexpected unindent. Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
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- 16 Dec, 2019 8 commits
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György Szing authored
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Bence Szépkúti authored
SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX on AArch32 when the arch-specific headers were merged. This value is not currently used by upstream TF-A source code, so no functionality should be affected. Change-Id: I2acf7f8736423697c7377e8ed4b08843ced26e66 Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
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Sandrine Bailleux authored
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Soby Mathew authored
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Sandrine Bailleux authored
Change-Id: Ia4faf873f8946992737f76870ac92bc5cb3f4020 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
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Justin Chadwell authored
-Wpadded warns whenever the C compiler automatically includes any padding in a structure. Because TF-A has a large number of structures, this occurs fairly frequently and is incredibly verbose, and as such is unlikely to ever be fixed. The utility of this warning is also extremely limited - knowing that a structure includes padding does not point to the existence of an error, and is probably quite unlikely to indicate actually buggy behaviour. Therefore, it's probably best to keep this warning off at all times. Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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Sandrine Bailleux authored
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- 14 Dec, 2019 10 commits
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Samuel Holland authored
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely independent. However, some H6 boards also need early regulator setup. Most of the register interface and all of the device tree traversal code can be reused between the AXP803 and AXP805. The main difference is the hardware bus interface, so that part is left to the platforms. The remainder is moved into a driver. I factored out the bits that were obviously specific to the AXP803; additional changes for compatibility with other PMICs can be made as needed. The only functional change is that rsb_init() now checks the PMIC's chip ID register against the expected value. This was already being done in the H6 version of the code. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
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Samuel Holland authored
This simplifies the code a bit. Verified to produce the same binary. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287
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Samuel Holland authored
As of a561e41b ("allwinner: power: add enable switches for DCDC1/5") there are no longer regulators without an enable register provided. Since it seems reasonable that this will continue to be the case, drop the check. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39
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Samuel Holland authored
should_enable_regulator() is already checked in the regulators subnode loop before setup_regulator() is called, so there's no need to check it again here. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977
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Samuel Holland authored
These are used by the PMIC setup code, which runs during BL31 initialization, and the PSCI shutdown code, also a part of BL31. They can't be needed before BL31, or it wouldn't be possible to boot. Allwinner platforms don't generally build anything but BL31 anyway, but this change improves clarity and consistency with allwinner-common.mk. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf
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Samuel Holland authored
The function is only used in this file, and it doesn't make sense for it to be used anywhere else. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f
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Samuel Holland authored
The action of last resort isn't going to change between SoCs. This moves that code back to the PSCI implementation, where it more obviously matches the code in sunxi_system_reset(). The two error messages say essentially the same thing anyway. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a
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Samuel Holland authored
- Check the return value from sunxi_init_platform_r_twi(). - Print the PMIC banner before doing anything that might fail. - Remove double prefixes in error messages. - Consistently omit the trailing period. - No need to print the unknown SoC's ID, since we already did that earlier in bl31_platform_setup(). - On the other hand, do print the ID of the unknown PMIC. - Try to keep the messages concise, as the large string size in these files was causing the firmware to spill into the next page. - Downgrade the banner from NOTICE to INFO. It's purely informational, and people should be using debug builds on untested hardware anyway. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb
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Samuel Holland authored
Ensure that the default (zero) value represents the case where we take no action. Previously, if a PLAT=sun50i_a64 build was booted on an unknown SoC ID, it would be treated as an H5 at shutdown. This removes some duplicate code and fixes error propagation on H6. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc
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Samuel Holland authored
The clock must be running for the module to be reset. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a
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- 13 Dec, 2019 6 commits
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Joshua Watt authored
Instead of stringizing the paths to binary files, add them as string defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR). This prevents macros from being expanded inside the string value itself. For example, -DFOO=/path/with-linux-in-it would have been expanded to "/path/with-1-in-it" because `linux=1` is one of the standard GCC defines. Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6 Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
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Soby Mathew authored
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Olivier Deprez authored
* changes: S-EL2 Support: Check for AArch64 Add support for enabling S-EL2
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Sandrine Bailleux authored
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Sandrine Bailleux authored
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Justin Chadwell authored
A function declaration declares the name of the function and the type of the parameter it returns. A function prototype is a function declaration that also specifies the type of the arguments of the function. Essentially, a function prototype helps the compiler ensure whether the function call matches the return type and the right number/type of arguments of function. A function prototype itself serves as a function declaration for new style functions. The warning flag -wmissing-prototype is good enough to check for missing function prototype and is exhaustive compared to -wmissing-declaration, therefore making the later redundant. Note that, at this point, these flags are part of WARNING1 which is not used for TF-A build by default. Several platforms use upstream libraries (such as zlib etc) which are in old style c code. After the TF-A build process is restructred using CMake framework, we plan to enable WARNING1, WARNING2 and WARNING3 incrementally as the new build platform can compile each BL binary of a particular platform with set of unique compilation flags. Change-Id: I9c6bf9da74e0840e4d2624bc12376e199953c213 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 12 Dec, 2019 4 commits
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Sandrine Bailleux authored
* changes: docs: tegra: add support for Tegra194 class of SoCs Tegra194: smmu: add support for backup multiple smmu regs Tegra194: introduce tegra_mc_def.h Tegra194: 40-bit wide memory address space Tegra194: psci: rename 'percpu_data' variable
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Soby Mathew authored
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Manish Pandey authored
When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead80 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818
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- 11 Dec, 2019 3 commits
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Gilad Ben-Yossef authored
Add the support needed to enable using CryptoCell integration with with RSA 3K support. Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com> Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17
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Alexei Fedorov authored
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Ambroise Vincent authored
This function scans a string backwards from the end for the first instance of a character. Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 10 Dec, 2019 5 commits
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Varun Wadekar authored
This patch adds the Tegra194 SoC information to the nvidia-tegra.rst file. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454
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Pritesh Raithatha authored
Tegra194 supports multiple SMMU blocks. This patch adds support to save register values for SMMU0 and SMMU2, before entering the System Suspend state. Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Pritesh Raithatha authored
This patch introduces memory controller register defines for Tegra194 platforms. Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Steven Kao authored
This patch updates the memory address space, physical and virtual, to be 40-bits wide for all Tegra194 platforms. Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c Signed-off-by: Steven Kao <skao@nvidia.com>
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Varun Wadekar authored
The per CPU wake times are saved in an array called 't19x_percpu_data'. But, there is one instance in the code where the name of the variable is misspelt. This patch fixes this typographical error to fix compilation errors. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
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