- 24 Mar, 2021 18 commits
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Pankaj Gupta authored
Chain of trust(CoT) is enabled on NXP SoC in two ways: - Using MbedTLS, parsing X509 Certificates. - Using NXP internal method parsing CSF header Signed-off-by:
Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by:
Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I78fb28516dfcfa667bebf8a1951ffb24bcab8de4
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Pankaj Gupta authored
NXP has hardware crypto accelerator called CAAM. - Work with Job ring - Jobs are submitted to CAAM in the form of 64 word descriptor. Signed-off-by:
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Pankaj Gupta authored
SD & eMMC driver support for NXP SoC. Signed-off-by:
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Pankaj Gupta authored
NXP QuadSPI driver support NXP SoC. - Supporting QSPI flash Signed-off-by: -
Kuldeep Singh authored
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs. Framework layer is currently embedded in driver itself using flash_info defines. Test cases are also added to confirm flash functionality currently under DEBUG flag. Signed-off-by:
Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
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Pankaj Gupta authored
GIC api used by NXP SoC is based on: - arm provided drivers: /drivers/arm/gic Signed-off-by: -
Pankaj Gupta authored
NXP General Purpose Input/Output driver support for NXP platforms. Signed-off-by: -
Pankaj Gupta authored
NXP Central Security Unit(CSU) for NXP SoC. CSU is used for: - Access permissions for peripheral that donot have their own access control. - Locking of individual CSU settings until the next POR - General purpose security related control bits Refer NXP SoC manuals fro more details. Signed-off-by: -
Pankaj Gupta authored
Driver for NXP IP for Power Management Unit. Signed-off-by: -
Pankaj Gupta authored
DDR driver for NXP layerscape SoC(s): - lx2160aqds - lx2162aqds - lx2160ardb - Other Board with SoC(s) like ls1046a, ls1043a etc; -- These other boards are not verified yet. Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by:
York Sun <york.sun@nxp.com> Signed-off-by:
Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by:
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Pankaj Gupta authored
NXP I2C driver support for NXP SoC(s). Signed-off-by:
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Pankaj Gupta authored
NXP Security Monitor IP provides hardware anchored - current security state of the SoC. - Tamper detect etc. Signed-off-by:
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Pankaj Gupta authored
NXP Security Fuse Processor is used to read and write fuses. - Fuses once written, are cannot be un-done. - Used as trust anchor for monotonic counter, different platform keys etc. Signed-off-by:
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Pankaj Gupta authored
CCN API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCN driver - driver/arm/ccn CCI API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCI driver - driver/arm/cci Signed-off-by: -
Pankaj Gupta authored
NXP TZC-400 API(s) to configure ddr regions are based on: - drivers/arm/tzc Signed-off-by: -
Pankaj Gupta authored
NXP Timer Apis are based on: - drivers/delay_timer Signed-off-by: -
Pankaj Gupta authored
NXP SoC needs Device Configuration driver to fetch the current SoC configuration. Signed-off-by: -
Pankaj Gupta authored
NXP SoCs, supports two types of UART controller: - PL011 - using ARM drivers sources - 16550 - using TI drivers source Signed-off-by:
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