1. 19 Jan, 2018 3 commits
  2. 12 Dec, 2017 1 commit
    • Julius Werner's avatar
      Add new function-pointer-based console API · 9536bae6
      Julius Werner authored
      
      
      This patch overhauls the console API to allow for multiple console
      instances of different drivers that are active at the same time. Instead
      of binding to well-known function names (like console_core_init),
      consoles now provide a register function (e.g. console_16550_register())
      that will hook them into the list of active consoles. All console
      operations will be dispatched to all consoles currently in the list.
      
      The new API will be selected by the build-time option MULTI_CONSOLE_API,
      which defaults to ${ERROR_DEPRECATED} for now. The old console API code
      will be retained to stay backwards-compatible to older platforms, but
      should no longer be used for any newly added platforms and can hopefully
      be removed at some point in the future.
      
      The new console API is intended to be used for both normal (bootup) and
      crash use cases, freeing platforms of the need to set up the crash
      console separately. Consoles can be individually configured to be active
      active at boot (until first handoff to EL2), at runtime (after first
      handoff to EL2), and/or after a crash. Console drivers should set a sane
      default upon registration that can be overridden with the
      console_set_scope() call. Code to hook up the crash reporting mechanism
      to this framework will be added with a later patch.
      
      This patch only affects AArch64, but the new API could easily be ported
      to AArch32 as well if desired.
      
      Change-Id: I35c5aa2cb3f719cfddd15565eb13c7cde4162549
      Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      9536bae6
  3. 21 Nov, 2017 1 commit
  4. 13 Nov, 2017 2 commits
    • Jeenu Viswambharan's avatar
      GIC: Fix Group 0 enabling · 385f1dbb
      Jeenu Viswambharan authored
      
      
      At present, the GIC drivers enable Group 0 interrupts only if there are
      Secure SPIs listed in the interrupt properties/list. This means that,
      even if there are Group 0 SGIs/PPIs configured, the group remained
      disabled in the absence of a Group 0 SPI.
      
      Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
      corresponding SGIs/PPIs are present.
      
      Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      385f1dbb
    • Jeenu Viswambharan's avatar
      GICv2: Fix populating PE target data · 058efeef
      Jeenu Viswambharan authored
      
      
      This patch brings in the following fixes:
      
        - The per-PE target data initialized during power up needs to be
          flushed so as to be visible to other PEs.
      
        - Setup per-PE target data for the primary PE as well. At present,
          this was only setup for secondary PEs when they were powered on.
      
      Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      058efeef
  5. 08 Nov, 2017 1 commit
    • Etienne Carriere's avatar
      ARMv7: GICv2 driver can manage GICv1 with security extension · 64deed19
      Etienne Carriere authored
      
      
      Some SoCs integrate a GIC in version 1 that is currently not supported
      by the trusted firmware. This change hijacks GICv2 driver to handle the
      GICv1 as GICv1 is compatible enough with GICv2 as far as the platform
      does not attempt to play with virtualization support or some GICv2
      specific power features.
      
      Note that current trusted firmware does not use these GICv2 features
      that are not available in GICv1 Security Extension.
      
      Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      64deed19
  6. 16 Oct, 2017 12 commits
  7. 06 Oct, 2017 1 commit
  8. 05 Oct, 2017 4 commits
    • Soby Mathew's avatar
      GICv3: ITS architectural save and restore helpers · b258278e
      Soby Mathew authored
      
      
      This patch adds functions to save and restore GICv3 ITS registers during
      system suspend. Please note that the power management of GIC ITS is
      implementation defined. These functions only implements the
      architectural part of the ITS power management and they do not restore
      memory structures or register content required to support ITS. Even if
      the ITS implementation stores structures in memory, an implementation
      defined power down sequence is likely to be required to flush some
      internal ITS caches to memory. If such implementation defined sequence
      is not followed, the platform must ensure that the ITS is not power
      gated during system suspend.
      
      Change-Id: I5f31e5541975aa7dcaab69b0b7f67583c0e27678
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      b258278e
    • Soby Mathew's avatar
      GICv3: add functions for save and restore · ebf1ca10
      Soby Mathew authored
      
      
      During system suspend, the GICv3 Distributor and Redistributor context
      can be lost due to power gating of the system power domain. This means
      that the GICv3 context needs to be saved prior to system suspend and
      restored on wakeup. Currently the consensus is that the Firmware should
      be in charge of this. See tf-issues#464 for more details.
      
      This patch introduces helper APIs in the GICv3 driver to save and
      restore the Distributor and Redistributor contexts. The GICv3 ITS
      context is not considered in this patch because the specification says
      that the details of ITS power management is implementation-defined.
      These APIs are expected to be appropriately invoked by the platform
      layer during system suspend.
      
      Fixes ARM-software/tf-issues#464
      
      Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      ebf1ca10
    • Douglas Raillard's avatar
      GICv3: turn some macros into inline functions · a64b4e62
      Douglas Raillard authored
      
      
      Tidy up the code a bit by turning some macros into inline functions
      which allows to remove the do/while(0) idiom and backslashes at the end
      of the line.
      
      Change-Id: Ie41a4ea4a4da507f7b925247b53e85019101d717
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      a64b4e62
    • Douglas Raillard's avatar
      GICv3: Fix gic600.c indentation · b50bdcea
      Douglas Raillard authored
      
      
      Reindent the file using tabs as the mix of spaces and tabs confuses some
      editors and leads them to use spaces instead of tabs for new code
      although the coding style mandates tabs.
      
      Change-Id: I87fa4a5d368a048340054b9b3622325f3f7befba
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      b50bdcea
  9. 22 Sep, 2017 2 commits
  10. 21 Sep, 2017 1 commit
    • Antonio Nino Diaz's avatar
      Fix type of `unsigned long` constants · e47ac1fd
      Antonio Nino Diaz authored
      
      
      The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
      AArch64. This is inconsistent and that's why we avoid using it as per
      the Coding Guidelines. This patch changes all `UL` occurrences to `U`
      or `ULL` depending on the context so that the size of the constant is
      clear.
      
      This problem affected the macro `BIT(nr)`. As long as this macro is used
      to fill fields of registers, that's not a problem, since all registers
      are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the
      macro is used to fill the fields of a 64-bit integer, it won't be able
      to set the upper 32 bits in AArch32.
      
      By changing the type of this macro to `unsigned long long` the behaviour
      is always the same regardless of the architecture, as this type is
      64-bit wide in both cases.
      
      Some Tegra platform files have been modified by this patch.
      
      Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      e47ac1fd
  11. 31 Aug, 2017 2 commits
    • Soby Mathew's avatar
      cert_tool: Support for legacy RSA PKCS#1 v1.5 · a8eb286a
      Soby Mathew authored
      
      
      This patch enables choice of RSA version at run time to be used for
      generating signatures by the cert_tool. The RSA PSS as defined in
      PKCS#1 v2.1 becomes the default version and this patch enables to specify
      the RSA PKCS#1 v1.5 algorithm to `cert_create` through the command line
      -a option. Also, the build option `KEY_ALG` can be used to pass this
      option from the build system. Please note that RSA PSS is mandated
      by Trusted Board Boot requirements (TBBR) and legacy RSA support is
      being added for compatibility reasons.
      
      Fixes ARM-Software/tf-issues#499
      Change-Id: Ifaa3f2f7c9b43f3d7b3effe2cde76bf6745a5d73
      Co-Authored-By: default avatarEleanor Bonnici <Eleanor.bonnici@arm.com>
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      a8eb286a
    • Soby Mathew's avatar
      Export KEY_ALG as a user build option · 2091755c
      Soby Mathew authored
      
      
      The `KEY_ALG` variable is used to select the algorithm for key
      generation by `cert_create` tool for signing the certificates. This
      variable was previously undocumented and did not have a global default
      value. This patch corrects this and also adds changes to derive the
      value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the
      platform. The corresponding assignment of these variables are also now
      removed from the `arm_common.mk` makefile.
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4
      2091755c
  12. 09 Aug, 2017 1 commit
  13. 01 Aug, 2017 2 commits
    • Jeenu Viswambharan's avatar
      Add SMMUv3 driver · 1154586b
      Jeenu Viswambharan authored
      
      
      The driver has only one API: to initialize an SMMUv3 device. This
      operates on a device that implements secure state, by invalidating
      secure caches and TLBs.
      
      Change-Id: Ief32800419ddf0f1fe38c8f0da8f5ba75c72c826
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      1154586b
    • Jeenu Viswambharan's avatar
      CCI: Adapt for specific product at run time · e33fd445
      Jeenu Viswambharan authored
      
      
      The current build system and driver requires the CCI product to be
      specified at build time. The device constraints can be determined at run
      time from its ID registers, obviating the need for specifying them
      ahead.
      
      This patch adds changes to identify and validate CCI at run time. Some
      global variables are renamed to be in line with the rest of the code
      base.
      
      The build option ARM_CCI_PRODUCT_ID is now removed, and user guide is
      updated.
      
      Change-Id: Ibb765e349d3bc95ff3eb9a64bde1207ab710a93d
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      e33fd445
  14. 12 Jul, 2017 1 commit
    • Isla Mitchell's avatar
      Fix order of #includes · 2a4b4b71
      Isla Mitchell authored
      
      
      This fix modifies the order of system includes to meet the ARM TF coding
      standard. There are some exceptions in order to retain header groupings,
      minimise changes to imported headers, and where there are headers within
      the #if and #ifndef statements.
      
      Change-Id: I65085a142ba6a83792b26efb47df1329153f1624
      Signed-off-by: default avatarIsla Mitchell <isla.mitchell@arm.com>
      2a4b4b71
  15. 28 Jun, 2017 2 commits
    • Soby Mathew's avatar
      Do basic CryptoCell LCS check · fd2b42f4
      Soby Mathew authored
      
      
      This patch implements the basic lifecycle state check when CryptoCell
      SBROM is initialized. Currently the check ensures that if the lifecycle
      state is Security Disabled (SD), the boot process does not proceed
      further.
      
      Change-Id: I5101335453cd3ea413e97bcfb9138a96c05e1aea
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      fd2b42f4
    • Soby Mathew's avatar
      Add CC crypto driver to the Auth module · 4eb20d99
      Soby Mathew authored
      
      
      This patch adds a crypto driver which utilizes the ARM® TrustZone®
      CryptoCell-712 to verify signature and hash during Trusted Board Boot. Along
      with this driver, the CryptoCell SBROM library is required to successfully
      build the BL image. The path to this library is specified via
      the `CCSBROM_LIB_PATH` variable. Please note that, mbedTLS is still required
      to do the X509 certificate ASN.1 parsing and CryptoCell is only utilized for
      signature and hash verification.
      
      Change-Id: If82dfbae0d7772ba1c64839f0b27850c103fe253
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      4eb20d99
  16. 23 Jun, 2017 3 commits
  17. 13 Jun, 2017 1 commit