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  1. 28 Sep, 2018 1 commit
  3. 30 Aug, 2018 5 commits
  5. 26 Jul, 2018 1 commit
  7. 12 Jun, 2018 2 commits
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 2 · 896a5902
      Daniel Boulby authored 
      

Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      896a5902
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.1 · 87d3aacc
      Daniel Boulby authored 
      

Rule 5.1: External identifiers shall be distinct

Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.

Fixed for:
    LOG_LEVEL=50 PLAT=fvp

Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      87d3aacc
  9. 03 Apr, 2018 1 commit
    • Andre Przywara's avatar
      gicv3: Fix support for systems without secure interrupts · 205cf6e7
      Andre Przywara authored 
      

Accessing the interrupt_props array only happens inside a loop over
interrupt_props_num, so the GICv3 driver can cope with no secure
interrupts. This allows us to relax the asserts that insists on
a non-NULL interrupt_props pointer and at least one secure interrupt.
This enables GICv3 platforms which have no need for a secure interrupt.

This only covers the non-deprecated code paths.

Change-Id: I49db291906512f56af065772f69acb281dfbdcfb
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      205cf6e7
  11. 26 Mar, 2018 2 commits
  13. 01 Mar, 2018 1 commit
    • Dan Handley's avatar
      Emit warnings when using deprecated GIC init · dcf01a0a
      Dan Handley authored 
      

Emit runtime warnings when intializing the GIC drivers using the
deprecated method of defining integer interrupt arrays in the GIC driver
data structures; interrupt_prop_t arrays should be used instead. This
helps platforms detect that they have migration work to do. Previously,
no warning was emitted in this case. This affects both the GICv2 and GICv3
drivers.

Also use the __deprecated attribute to emit a build time warning if these
deprecated fields are used. These warnings are suppressed in the GIC
driver compatibility functions but will be visible if platforms use them.

Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a
Signed-off-by: default avatarDan Handley <dan.handley@arm.com>
      dcf01a0a
  15. 28 Feb, 2018 1 commit
  17. 24 Jan, 2018 1 commit
  19. 13 Nov, 2017 1 commit
    • Jeenu Viswambharan's avatar
      GIC: Fix Group 0 enabling · 385f1dbb
      Jeenu Viswambharan authored 
      

At present, the GIC drivers enable Group 0 interrupts only if there are
Secure SPIs listed in the interrupt properties/list. This means that,
even if there are Group 0 SGIs/PPIs configured, the group remained
disabled in the absence of a Group 0 SPI.

Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
corresponding SGIs/PPIs are present.

Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      385f1dbb
  21. 16 Oct, 2017 11 commits
  23. 06 Oct, 2017 1 commit
  25. 05 Oct, 2017 4 commits
    • Soby Mathew's avatar
      GICv3: ITS architectural save and restore helpers · b258278e
      Soby Mathew authored 
      

This patch adds functions to save and restore GICv3 ITS registers during
system suspend. Please note that the power management of GIC ITS is
implementation defined. These functions only implements the
architectural part of the ITS power management and they do not restore
memory structures or register content required to support ITS. Even if
the ITS implementation stores structures in memory, an implementation
defined power down sequence is likely to be required to flush some
internal ITS caches to memory. If such implementation defined sequence
is not followed, the platform must ensure that the ITS is not power
gated during system suspend.

Change-Id: I5f31e5541975aa7dcaab69b0b7f67583c0e27678
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      b258278e
    • Soby Mathew's avatar
      GICv3: add functions for save and restore · ebf1ca10
      Soby Mathew authored 
      

During system suspend, the GICv3 Distributor and Redistributor context
can be lost due to power gating of the system power domain. This means
that the GICv3 context needs to be saved prior to system suspend and
restored on wakeup. Currently the consensus is that the Firmware should
be in charge of this. See tf-issues#464 for more details.

This patch introduces helper APIs in the GICv3 driver to save and
restore the Distributor and Redistributor contexts. The GICv3 ITS
context is not considered in this patch because the specification says
that the details of ITS power management is implementation-defined.
These APIs are expected to be appropriately invoked by the platform
layer during system suspend.

Fixes ARM-software/tf-issues#464

Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      ebf1ca10
    • Douglas Raillard's avatar
      GICv3: turn some macros into inline functions · a64b4e62
      Douglas Raillard authored 
      

Tidy up the code a bit by turning some macros into inline functions
which allows to remove the do/while(0) idiom and backslashes at the end
of the line.

Change-Id: Ie41a4ea4a4da507f7b925247b53e85019101d717
Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      a64b4e62
    • Douglas Raillard's avatar
      GICv3: Fix gic600.c indentation · b50bdcea
      Douglas Raillard authored 
      

Reindent the file using tabs as the mix of spaces and tabs confuses some
editors and leads them to use spaces instead of tabs for new code
although the coding style mandates tabs.

Change-Id: I87fa4a5d368a048340054b9b3622325f3f7befba
Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      b50bdcea
  27. 01 Jun, 2017 1 commit
    • Jeenu Viswambharan's avatar
      Introduce ARM GIC-600 driver · e1c59ab3
      Jeenu Viswambharan authored 
      

ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame. This
register must be programmed to mark the frame as powered on, before
accessing other registers in the frame. Rest of initialization sequence
remains the same.

The driver provides APIs for Redistributor power management, and
overrides those in the generic GICv3 driver. The driver data is shared
between generic GICv3 driver and that of GIC-600.

For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER
is set to FVP_GIC600. Also update user guide.

Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      e1c59ab3
  29. 03 May, 2017 1 commit
  31. 01 Mar, 2017 1 commit
    • Soby Mathew's avatar
      Flush the GIC driver data after init · 311b1773
      Soby Mathew authored 
      

The GIC driver data is initialized by the primary CPU with caches
enabled. When the secondary CPU boots up, it initializes the
GICC/GICR interface with the caches disabled and there is a chance that
the driver data is not yet written back to the memory. This patch fixes
this problem by flushing the driver data after they have been
initialized.

Change-Id: Ie9477029683846209593ff005d2bac559bb8f5e6
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      311b1773
  33. 15 Dec, 2016 1 commit
  35. 12 Sep, 2016 1 commit
    • Yatharth Kochar's avatar
      GICv3: Allow either G1S or G0 interrupts to be configured · 6083c841
      Yatharth Kochar authored 
      Currently the GICv3 driver mandates that platform populate
both G1S and G0 interrupts. However, it is possible that a
given platform is not interested in both the groups and
just needs to specify either one of them.

This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()`
functions to allow either G1S or G0 interrupts to be configured.

Fixes ARM-software/tf-issues#400

Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b
      6083c841
  37. 11 Aug, 2016 1 commit
    • Sudeep Holla's avatar
      gicv3: disable Group1 NonSecure interrupts during core powerdown · 65d68ca6
      Sudeep Holla authored 
      As per the GICv3 specification, to power down a processor using GICv3
and allow automatic power-on if an interrupt must be sent to a processor,
software must set Enable to zero for all interrupt groups(by writing to
GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.

Also, NonSecure EL1 software may not be aware of the CPU power state
details and fail to choose right states that require quiescing the CPU
interface. So it's preferred that the PSCI implementation handles it as
it is fully aware of the CPU power states.

This patch adds disabling of Group1 NonSecure interrupts during processor
power down along with Group0 and Group1 Secure interrupts so that all the
interrupt groups are handled at once as per specification.

Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641
      65d68ca6
  39. 10 Aug, 2016 1 commit
    • Soby Mathew's avatar
      AArch32: Enable GIC and TZC support · 367d0ffb
      Soby Mathew authored 
      This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes that the secure world is running in Little-Endian
mode to do 64 bit manipulations. Assertions are present to validate the
assumption.

Note: The legacy GICv3 driver is not supported for AArch32.

Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
      367d0ffb
  41. 27 Jul, 2016 1 commit
    • Soby Mathew's avatar
      GICv3: Fix the GICD_IROUTER offset · 61e30277
      Soby Mathew authored 
      This patch fixes the offset of GICD_IROUTER register defined in gicv3.h.
Although the GICv3 documention mentions that the offset for this register
is 0x6100-0x7FD8, the offset calculation for an interrupt id `n` is :

   0x6000 + 8n, where n >= 32

This requires the offset for GICD_IROUTER to be defined as 0x6000.

Fixes ARM-software/tf-issues#410

Change-Id: If9e91e30d946afe7f1f60fea4f065c7567093fa8
      61e30277