- 14 Dec, 2020 1 commit
-
-
Samuel Holland authored
While the Allwinner platform code nominally supported a custom PRELOADED_BL33_BASE, some references to the BL33 load address used another constant: PLAT_SUNXI_NS_IMAGE_OFFSET. To allow the DTB search code to work if a U-Boot BL33 is loaded to a custom address, consistently use PRELOADED_BL33_BASE. And to avoid this confusion in the future, remove the other constant. Signed-off-by:Samuel Holland <samuel@sholland.org> Change-Id: Ie6b97ae1fdec95d784676aef39200bef161471b0
-
- 09 Dec, 2020 4 commits
-
-
Manish Pandey authored
* changes: plat: xilinx: versal: Add support of register notifier plat: xilinx: versal: Add support to get clock rate value plat: xilinx: versal: Add support of set max latency for the device plat: versal: Add InitFinalize API call xilinx: versal: Updated Response of QueryData API call plat:xilinx:versal: Use defaults when PDI is without sw partitions plat: xilinx: Mask unnecessary bytes of return error code xilinx: versal: Skip store/restore of GIC during CPU idle plat: versal: Update API list in feature check xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
-
Olivier Deprez authored
* changes: spm: provide number of vCPUs and VM size for first SP spm: remove chosen node from SPMC manifests spm: move OP-TEE SP manifest DTS to FVP platform spm: update OP-TEE SP manifest with device-regions node spm: remove device-memory node from SPMC manifests
-
Olivier Deprez authored
-
Manish V Badarkhe authored
Updated the documentation for the FIP generation process using SP images. Change-Id: I4df7f379f08f33adba6f5c82904291576972e106 Signed-off-by:Manish V Badarkhe <Manish.Badarkhe@arm.com>
-
- 08 Dec, 2020 11 commits
-
-
Manish Pandey authored
-
Manish Pandey authored
* changes: zynqmp: pm: Update flags in common clk divisor node zynqmp: pm_api_clock: Copy only the valid bytes
-
Marek Vasut authored
The BL31 log driver is registered before the xlat tables are initialized, at that point the log memory is configured as device memory and can only be accessed with up-to-32bit aligned accesses. Adjust the driver to do just that. The memset() call has to be replaced by a loop of 32bit writes to the log, the memcpy() is trivial to replace with a single 32bit write of the entire TLOG word. In the end, this even simplifies the code. Signed-off-by:Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
-
Ravi Patel authored
Current implementation doesn't support change of div1 value if clk has 2 divisor because div1 clk is the parent of the div2 clk and div2 clk does not have SET_RATE_PARENT flag. This causes div1 value to be fixed and only value of div2 will be adjusted according to required clock rate. Example: Consider a case of nand_ref clock which has 2 divisor and 1 mux. The frequency of mux clock is 1500MHz and default value of div1 and div2 is 15 and 1 respectively. So the final clock will be of 100MHz. When driver requests 80MHz for nand_ref clock, clock framework will adjust the div2 value to 1 (setting div2 value 2 results final clock to 50MHz which is more inaccurate compare to 100Mhz) which results final clock to 100MHz. Ideally the value of div1 and div2 should be updated to 19 and 1 respectively so that final clock goes to around 78MHz. This patch fixes above problem by allowing change in div1 value. Signed-off-by:
Ravi Patel <ravi.patel@xilinx.com> Signed-off-by:
Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
-
Siva Durga Prasad Paladugu authored
This patches copies only the valid part of string and avoids filling junk at the end. Signed-off-by:
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by:
-
Manish Pandey authored
* changes: mediatek: mt8192: dcm: Add mcusys related dcm drivers mediatek: mt8192: add ptp3 driver mediatek: mt8192: Add SiP service mediatek: mt8192: add uart save and restore api mediatek: mt8192: modify sys_cirq driver mediatek: mt8192: add power-off support mediatek: mt8192: add pmic mt6359p driver mediatek: mt8192: Initialize delay_timer mediatek: mt8192: enable NS access for systimer mediatek: mt8192: Add CPU hotplug and MCDI support mediatek: mt8192: Add MCDI drivers mediatek: mt8192: Add SPMC driver
-
Olivier Deprez authored
The primary VM concept is removed from the SPMC. Update the SPMC manifests with number of Execution Contexts and SP workspace size for the first Secure Partition (as it is done for NWd secondary VMs and other SPs). Signed-off-by:Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3b9c52666f7dfe74ab1f7d2148ad0070ee44b54e
-
Olivier Deprez authored
The chosen node is no longer required as the SPMC implements a specific boot flow which no longer requires this node. Signed-off-by: -
Olivier Deprez authored
Signed-off-by: -
Olivier Deprez authored
Specify peripherals accessed by OP-TEE as a Secure Partition running as a VM managed by the SPMC. Signed-off-by: -
Olivier Deprez authored
The PVM concept is removed from the SPMC so the device-memory node which is specifying the device memory range for the PVM is no longer applicable. Signed-off-by:
-
- 07 Dec, 2020 24 commits
-
-
Nina Wu authored
1. Add mcusys related dcm drivers 2. Turn on mcusys-related dcm by default Change-Id: Ibbee37c87cc38e7a6cd7c93c2fc0817aad6dbe95 Signed-off-by:Nina Wu <nina-cm.wu@mediatek.com>
-
elly.chiang authored
enable PTP3 for protecting sysPi Signed-off-by:elly.chiang <elly.chiang@mediatek.com> Change-Id: Ic3a13c8314f829dca8547861b98639d1d9444eb2
-
Nina Wu authored
Add the basic SiP service Change-Id: Ib7f2380aab910adf8d33498a79ecd287273907c5 Signed-off-by: -
Yuchen Huang authored
When system resume, we want to print log as soon as possible. So we add uart save and restore api, and they will be called when systtem suspend and resume. Change-Id: I83b477fd2b39567c9c6b70534ef186993f7053ae Signed-off-by:
Yuchen Huang <yuchen.huang@mediatek.com> Signed-off-by:
Roger Lu <roger.lu@mediatek.com>
-
G.Pangao authored
1.Modify this driver to make it more complete and more standard. 2.And makes this driver available for more IC services. 3.Solve some bugs in the software. Signed-off-by:G.Pangao <gtk_pangao@mediatek.com> Change-Id: I284956d47ebbbd550ec93767679181185e442348
-
Hsin-Hsiung Wang authored
add power-off support Signed-off-by:Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: If19e99971515a8ae1ac9ae21046e4382adc18a69
-
Hsin-Hsiung Wang authored
add pmic mt6359p driver Signed-off-by: -
Nina Wu authored
Init delay_timer for the use of delay functions Change-Id: I35aefd7515bb9259634c8b6bc37d8c74da96e8f1 Signed-off-by: -
Dehui Sun authored
Enable NS access for all systimers. Signed-off-by:Dehui Sun <dehui.sun@mediatek.com> Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a
-
James Liao authored
Implement PSCI platform OPs to support CPU hotplug and MCDI. Change-Id: I31abfc752b69ac40e70bc9e7a55163eb39776c44 Signed-off-by:James Liao <jamesjj.liao@mediatek.com>
-
James Liao authored
Add MCDI related drivers to handle CPU powered on/off in CPU suspend. Change-Id: I5110461e8eef86f8383b45f197ec5cb10dbfeb3e Signed-off-by: -
James Liao authored
Add SPMC driver for CPU power on/off. Change-Id: I526b98d5885855efce019dd09cfd93b8816cbf19 Signed-off-by: -
Madhukar Pappireddy authored
* changes: plat: xilinx: zynqmp: Enable log messages for debug plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
-
Manish Pandey authored
* changes: plat: marvell: armada: a3k: Simplify check if WTP variable is defined plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL) plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB plat: marvell: armada: Add missing FORCE, .PHONY and clean targets plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG) plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
-
Tejas Patel authored
Add support of register notifier. Signed-off-by:
Tejas Patel <tejas.patel@xilinx.com> Signed-off-by:
-
Tejas Patel authored
Add support to get clock's rate value. Signed-off-by:
-
Tejas Patel authored
Add support of set max latency, to change in the maximum powerup latency requirements for a specific device currently used by Subsystem. Signed-off-by:
-
Ravi Patel authored
Add support to call InitFinalize API in Versal which calls corresponding LibPM API. Signed-off-by:
-
Rajan Vaja authored
For the current XilPM calls, The handler of IPI returns information with 16 Bytes data. So during QueryData API call for the ClockName and PinFunctionName, response data(name of clock or function) response[0..3] are used to return name. And status is not being returned for such API. Updated XilPM calls reply in a consistent way and The handler of IPI return information with 32Bytes data. Where response[0] always set to status. For the version-2 of QueryData API, during call for the ClockName and PinFunctionName, response data(name of clock or function) get as response[1...4]. To support both the version of QueryData API, added version based compatibility by the use of feature check. Signed-off-by:
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by:
Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com> Signed-off-by:
-
Venkatesh Yadav Abbarapu authored
In JTAG mode check the ATF handoff structure, if the magic string is not present then use bl32 and bl33 default values. Signed-off-by:
-
Ravi Patel authored
Versal firmware adds extra error codes along with PM error codes while sending response to driver. This makes incorrect error identification at driver side. To fix this, mask the unnecessary error bytes before sending the error code to the driver. Signed-off-by:
-
Ravi Patel authored
GIC registers needs to be stored/restored during system suspend/resume only and not during CPU idle. During CPU idle, minimum 1 CPU is in ON state. Signed-off-by:
-
Venkatesh Yadav Abbarapu authored
Add below API in feature check list which is actually present in firmware: - PM_GET_CHIPID Signed-off-by:
-
Ravi Patel authored
Existing code passes ACPU0 to LibPM as node_id in set_wakeup_source() call because last suspending core will be ACPU0 in most of the case. Now it may be possible that user may disable the ACPU0 using hot-plug and after that it suspends Linux. So in that case ACPU0 will not be last suspending core. To overcome above scenario, pass the current running processor ID while calling set_wakeup_source(). Signed-off-by:
-
