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  1. 06 Apr, 2021 3 commits
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization · 40d08192
      Pali Rohár authored 
      

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
      40d08192
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call · ccec1bd5
      Pali Rohár authored 
      

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
  new_val = (old_val & ~mask) | (data & mask);
it does
  new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
 since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
      ccec1bd5
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Fix configuring polarity invert bits · ee4c70eb
      Pali Rohár authored 
      

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
      ee4c70eb
  3. 24 Mar, 2021 19 commits
  5. 19 Mar, 2021 1 commit
  7. 17 Mar, 2021 1 commit
    • deqi.hu's avatar
      mmc:prevent accessing to the released space in case of wrong usage · 13f3c516
      deqi.hu authored 
      1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
  In order to avoid referencing the released space on the stack when maybe MISUSED,
  it`s better to use global variables to store mmc_device_info in mmc.c
2.Delete redundant;

Signed-off-by: deqi.hu@siengine.com
Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
      13f3c516
  9. 16 Feb, 2021 3 commits
    • Pali Rohár's avatar
      marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms · 0d06b058
      Pali Rohár authored 
      

TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so wait at least 3ms
before flushing TX FIFO.

If WTMI firmware transmitted something via UART before TF-A was booted,
some characters may still wait in TX FIFO when TF-A is initializing UART
driver. So wait at least 3ms to ensure that HW has enough time to transmit
all characters waiting in TX FIFO.

This fixes an issue where sometimes characters transmitted on UART by our
custom WTMI image are lost.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19
      0d06b058
    • Pali Rohár's avatar
      marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU · 98641515
      Pali Rohár authored 
      

Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to
wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720
CPU is 600 MHz and in this case delay loop would take just 2 times more,
which is not a problem.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2
      98641515
    • Pali Rohár's avatar
      marvell: uart: a3720: Fix comments in console_a3700_core_init() function · ab1fe188
      Pali Rohár authored 
      

The delay loop executes 3 instructions. These 3 instructions are executed
in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield
approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX
FIFO to be empty.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f
      ab1fe188
  11. 11 Feb, 2021 6 commits
  13. 09 Feb, 2021 1 commit
    • Heyi Guo's avatar
      tzc400: adjust filter flag if it is set to FILTER_BIT_ALL · d4c61c38
      Heyi Guo authored 
      

TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
it can't get the real filter number to construct the bit flag for all
existing filters. If the platform doesn't have 4 filters, passing
FILTER_BIT_ALL to tzc400_configure_region() will cause assertion or
misconfiguration. So adjust the bit flag against the real filter
number.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie5c48303485f3b5015772961ee7c34746121ee84
      d4c61c38
  15. 03 Feb, 2021 6 commits
    • Heyi Guo's avatar
      drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64() · 612b4a3f
      Heyi Guo authored 
      

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSET_64() is only used for
GICD_IROUTER<E>, and IROUTER_SHIFT is 0.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d
      612b4a3f
    • Heyi Guo's avatar
      drivers/gicv3: add debug log for maximum INTID of SPI and eSPI · 705032de
      Heyi Guo authored 
      

Add debug log for the maximum supported INTID of SPI and eSPI on the
current GIC implementation.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Ie45ab1d85b39658c4ca4bc54ee433ac44e41d03f
      705032de
    • Heyi Guo's avatar
      drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET() · 4e42c227
      Heyi Guo authored 
      

The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
the maximum possible value for num_ints is 1024. The value must be
limited to (MAX_SPI_ID + 1), or GICD_OFFSET() will consider it as ESPI
INTID and return wrong register address.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iddcb83d3e5d241b39f4176c19c2bceaa2c3dd653
      4e42c227
    • Heyi Guo's avatar
      drivers/gicv3: fix logical issue for num_eints · 69ae4427
      Heyi Guo authored 
      

In function gicv3_spis_config_defaults(), the variable num_ints is set
to (maximum SPI INTID + 1), while num_eints is set to (maximum ESPI
INTID). It introduces not only inconsistency to the code, but also
logical bug in the "for" loops, for the INTID of num_eints is also
valid and the check should be inclusive.

Fix this by setting num_eints to (maximum ESPI INTID + 1) as well.

Fix similar issues in gicv3_distif_save() and
gicv3_distif_init_restore().
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I4425777d17e84e85f38853603340bd348640154f
      69ae4427
    • Heyi Guo's avatar
      drivers/gicv3: fix potential GICD context override with ESPI enabled · deb18901
      Heyi Guo authored 
      

RESTORE/SAVE_GICD_EREGS uses (int_id - (MIN_ESPI_ID - MIN_SPI_ID)) to
get the context array index for ESPI, which will override the space of
standard SPI starting from (MIN_SPI_ID + MIN_SPI_ID).

However, using TOTAL_SPI_INTR_NUM to replace the above MIN_SPI_ID
cannot totally fix the issue, for TOTAL_SPI_INTR_NUM is not well
aligned and the array index will be rounded down by the shifting
operation if being shifted more than 2 bits. It will cause buffer
override again when the existing maximum SPI reaches 1019.

So round up TOTAL_SPI_INTR_NUM with (1 << REG##R_SHIFT) for GICD
context arrays.
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5be2837c42f381a62f8d46a4ecd778009b1fe059
      deb18901
    • Heyi Guo's avatar
      drivers/gicv3: use mpidr to probe GICR for current CPU · 60cd8030
      Heyi Guo authored 
      

In function gicv3_rdistif_probe(), line #1322 implies
gicv3_driver_data->mpidr_to_core_pos() may be null, but the original
code uses this interface to get current CPU index unconditionally.

It is better to use MPIDR to probe GICR which does not depend on
gicv3_driver_data->mpidr_to_core_pos().
Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I64add055385040fe0a56b977e2299608e2309a6e
      60cd8030