- 17 Oct, 2018 1 commit
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Jorge Ramirez-Ortiz authored
Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
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- 10 Oct, 2018 2 commits
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John Tsichritzis authored
Change-Id: Icc6fb03abb9b4ef85931b9e3d767b5a9c271b5f3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
Change-Id: I1ce771a155e6e83885a00d2f05591bf98cd69854 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 03 Oct, 2018 2 commits
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Konstantin Porotchkin authored
The BLE is the pre-TF-A boot stage required by Marvell Armada BootROM for bringing up DRAM and allow the boot image copy to it. Since this is not a standard boot level and only uses the TF-A as a build environment, it was introduced out of source tree. However it turns out that such remote location introduces additional complexity to the upstream TF-A build process. In order to simplify the build environment the BLE source folder is relocated from the external repository to A8K platform directory. The build documentation is updated accordingly. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Daniel Boulby authored
This patch introduces a build flag "RECLAIM_INIT_CODE" to mark boot time code which allows platforms to place this memory in an appropriate section to be reclaimed later. This features is primarily targeted for BL31. Appropriate documentation updates are also done. Change-Id: If0ca062851614805d769c332c771083d46599194 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 02 Oct, 2018 4 commits
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Soby Mathew authored
Change-Id: I9d14faa7294578443233b84d5459fa7b62a30c07 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Antonio Nino Diaz authored
This option makes it hard to optimize the memory definitions of all Arm platforms because any change in the common defines must work in all of them. The best thing to do is to remove it and move the definition to each platform's header. FVP, SGI and SGM were using the definitions in board_arm_def.h. The definitions have been copied to each platform's platform_def.h. Juno was already using the ones in platform_def.h, so there have been no changes. Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Joanna Farley authored
Change-Id: Iaa5c586b65f0abdd4ddbdee4c73d07811a0aff49 Signed-off-by: Joanna Farley <joanna.farley@arm.com>
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Soby Mathew authored
Information regarding platform compatibility policy is added to the documentation. Change-Id: If9f2a11160f81354ee2c678f0fca9d67fc7366e6 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 01 Oct, 2018 1 commit
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Soby Mathew authored
Change-Id: I69e2720f534583a0f8d0e44f2e7b6f393f6fd093 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 28 Sep, 2018 7 commits
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Antonio Nino Diaz authored
- Remove references to removed build options. - Migrate to bl31_early_platform_setup2(). Change-Id: Ibeb8982a0a841f55ce778c4f09f06b72b47b21d8 Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I2885b0d8cb9bb16da1fa96a30e46cccde434dc42 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Roberto Vargas authored
The code of LOAD_IMAGE_V2=0 has been removed. Change-Id: Iea03e5bebb90c66889bdb23f85c07d0c9717fffe Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Roberto Vargas authored
Change-Id: I40d040aa05bcbf11536a96ce59827711456b93a8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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dp-arm authored
A compatibility script has been provided for about 2 years. Users should have migrated to fiptool by now so remove the compat script. Change-Id: I643e0c40a9e3fb428bad3be04a82cb431aad74dc Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 21 Sep, 2018 1 commit
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Joanna Farley authored
Change-Id: I7855c9d3de104975bf3249bdf291c428f001d07a Signed-off-by: Joanna Farley <joanna.farley@arm.com>
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- 20 Sep, 2018 2 commits
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Sandrine Bailleux authored
Change-Id: Ib9a045200de4fcd00387b114cbbd006e46ad6a8b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
Change-Id: Ia67a4786350c1c2ef55125cd6a318ae6d918c08e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 11 Sep, 2018 1 commit
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David Cunado authored
- Linaro binaries: 18.04 - mbed TLS library: 2.12.0 - FVP model versions: 11.4 build 37 This patch updates the user guide documentation to reflect these changes to the dependencies. Change-Id: I454782ca43a0db43aeeef2ab3622f4dea9dfec55 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 04 Sep, 2018 4 commits
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Bryan O'Donoghue authored
This patch describes the boot-flow and building of the WaRP7 TF-A port. What it describes is booting and unsigned TF-A. A very brief section has been added on signing BL2 which is in no-way comprehensive. For a comprehensive description of the signing process try the Boundary Devices blog on the matter. https://boundarydevices.com/high-assurance-boot-hab-dummies/ Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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John Tsichritzis authored
Change-Id: Ic58f88fa4e5fc0004a33357915ff80db30954441 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
This patch introduces the shared Mbed TLS heap optimisation for Arm platforms. The objective is the Mbed TLS heap to be shared between BL1 and BL2 so as to not allocate the heap memory twice. To achieve that, the patch introduces all the necessary helpers for implementing this optimisation. It also applies it for FVP. Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
The Mbed TLS drivers, in order to work, need a heap for internal usage. This heap, instead of being directly referenced by the drivers, now it is being accessed indirectly through a pointer. Also, the heap, instead of being part of the drivers, now it is being received through the plat_get_mbedtls_heap() function. This function requests a heap from the current BL image which utilises the Mbed TLS drivers. Those changes create the opportunity for the Mbed TLS heap to be shared among different images, thus saving memory. A default heap implementation is provided but it can be overridden by a platform specific, optimised implemenetation. Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 02 Sep, 2018 1 commit
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Konstantin Porotchkin authored
Update build manual - remove irrelevant platforms and environemnt variables - add links to BLE and mv_ddr Github repositories Change-Id: Ie389c61f014751cdc0459b3f78c70ede694d27b8 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 30 Aug, 2018 3 commits
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Douglas Raillard authored
This function diplays the backtrace, the current EL and security state to allow a post-processing tool to choose the right binary to interpret the dump. The output can be fed to GNU addr2line to resolve function names given an ELF binary compiled with debug information. The "-i" flag is recommended to improve display in case of inlined functions. The *.dump files generated during the build process can also be used. The function works in AArch64 and AArch32. In AArch32 it only works in A32 mode (without T32 interworking), which is enforced in the Makefile. Sample output of a backtrace at EL3: BACKTRACE: START: function_name 0: EL3: 0x798 1: EL3: 0x538 2: EL3: 0x550 3: EL3: 0x55c 4: EL3: 0x568 5: EL3: 0x5a8 6: EL3: 0xf4 BACKTRACE: END: function_name In order to enable it the new option ENABLE_BACKTRACE must be set to 1. This option is set to 1 by default only in AArch64 debug builds. As usual, it can be overridden by the platform makefile and in the build command line. Change-Id: Icaff39b0e5188329728be2f3c72b868b2368e794 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Antonio Nino Diaz authored
At the moment the AArch32 instruction set isn't specified in the command line, which means that the compiler is free to choose the one it sees fit. This decision may change between compiler versions, so it is better to specify it manually. The build option AARCH32_INSTRUCTION_SET has been introduced for this reason. This option can be set to T32 or A32 to pass the correct flags to the compiler. The current behaviour is to default to T32 due to it's smaller size. Change-Id: I02297eb1d9404b5868ff7c054fbff9b3cda7fdb6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Julius Werner authored
This patch fixes a bug in the context management code that causes it to ignore the HANDLE_EA_EL3_FIRST compile-time option and instead always configure SCR_EL3 to force all external aborts to trap into EL3. The code used #ifdef to read compile-time option declared with add_define in the Makefile... however, those options are always defined, they're just defined to either 0 or 1, so #if is the correct syntax to check for them. Also update the documentation to match. This bug has existed since the Nov 2017 commit 76454abf (AArch64: Introduce External Abort handling), which changed the HANDLE_EA_EL3_FIRST option to use add_define. Change-Id: I7189f41d0daee78fa2fcf4066323e663e1e04d3d Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 22 Aug, 2018 2 commits
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Antonio Nino Diaz authored
Change their names to printf and snprintf. They are much smaller than the previous versions we had, which makes them better suited for the Trusted Firmware. Change-Id: Ia872af91b7b967c47fce012eccecede7873a3daf Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Taken from http://git.simple-cc.org/scc/ from the following commit: 67508ad14af314cea2229783d3c084f28c41daf0 Permission has been granted from the author to use them under the license BSD-3-Clause instead of ISC. Change-Id: I65c0ce3ab60c49d34a57533af12a74bd7bde88e5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Aug, 2018 1 commit
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Jeenu Viswambharan authored
Memory Partitioning And Monitoring is an Armv8.4 feature that enables various memory system components and resources to define partitions. Software running at various ELs can then assign themselves to the desired partition to control their performance aspects. With this patch, when ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows lower ELs to access their own MPAM registers without trapping to EL3. This patch however doesn't make use of partitioning in EL3; platform initialisation code should configure and use partitions in EL3 if required. Change-Id: I5a55b6771ccaa0c1cffc05543d2116b60cbbcdcd Co-authored-by: James Morse <james.morse@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 17 Aug, 2018 2 commits
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John Tsichritzis authored
If the system is in near idle conditions, this erratum could cause a deadlock or data corruption. This patch applies the workaround that prevents this. This DSU erratum affects only the DSUs that contain the ACP interface and it was fixed in r2p0. The workaround is applied only to the DSUs that are actually affected. Link to respective Arm documentation: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Sathees Balya authored
Change-Id: Ice87052e41a24b0ede5610467e12941ae1d886e0 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 15 Aug, 2018 1 commit
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John Tsichritzis authored
Change-Id: I426ffc8717757e35e556f675162a729ba095b7d5 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 24 Jul, 2018 2 commits
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Yann Gautier authored
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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John Tsichritzis authored
Change-Id: Id2639218dfffec84d8b0fa295d7e896129d4fcd7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 19 Jul, 2018 1 commit
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Jeenu Viswambharan authored
Change-Id: I76cb1d387ab51ee48fa91fd7458c7041b454ceee Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 18 Jul, 2018 2 commits
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Konstantin Porotchkin authored
Change-Id: I341440701b7e5e3555e604dd9d0a356795e6c4fb Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add address decoding unit drivers for Marvell SoCs. Address decoding flow and address translation units chart are located at docs/marvell/misc/mvebu-a8k-addr-map.txt Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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