- 20 May, 2014 1 commit
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Lin Ma authored
Addresses were declared as "unsigned int" in drivers/arm/peripherals/pl011/pl011.h and in function init_xlation_table. Changed to use "unsigned long" instead Fixes ARM-software/tf-issues#156
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- 16 May, 2014 4 commits
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Andrew Thoelke authored
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Andrew Thoelke authored
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Andrew Thoelke authored
Change-Id: If8744c38c2d5c50caa7454b055e2ba418cf1e8bf
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danh-arm authored
Fixes for TZC configuration on FVP
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- 13 May, 2014 2 commits
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Sandrine Bailleux authored
On FVP, the file 'plat/fvp/aarch64/plat_helpers.S' contains an FVP-specific implementation of the function 'plat_report_exception()', which is meant to override the default implementation. However, this file was not included into the BL3-2 image, meaning it was still using the default implementation. This patch fixes the FVP makefile to compile this file in. Change-Id: I3d44b9ec3a9de7e2762e0887d3599b185d3e28d2
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Juan Castillo authored
This patch fixes C accessors to GIC registers that follow a set/clear semantic to change the state of an interrupt, instead of read/write/modify. These registers are: Set-Enable Clear-Enable Set-Pending Clear-Pending Set-Active Clear-Active For instance, to enable an interrupt we write a one to the corresponding bit in the Set-Enable register, whereas to disable it we write a one to the corresponding bit in the Clear-Enable register. Fixes ARM-software/tf-issues#137 Change-Id: I3b66bad94d0b28e0fe08c9042bac0bf5ffa07944
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- 12 May, 2014 1 commit
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Andrew Thoelke authored
The TZC configuration on FVP was incorrectly allowing both secure and non-secure accesses to the DRAM, which can cause aliasing problems for software. It was also not enabling virtio access on some models. This patch fixes both of those issues. The patch also enabless non-secure access to the DDR RAM for all devices with defined IDs. The third region of DDR RAM has been removed from the configuration as this is not used in any of the FVP models. Fixes ARM-software/tf-issues#150 Fixes ARM-software/tf-issues#151 Change-Id: I60ad5daaf55e14f178affb8afd95d17e7537abd7
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- 09 May, 2014 2 commits
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Sandrine Bailleux authored
Instead of having a single version of the MMU setup functions for all bootloader images that can execute either in EL3 or in EL1, provide separate functions for EL1 and EL3. Each bootloader image can then call the appropriate version of these functions. The aim is to reduce the amount of code compiled in each BL image by embedding only what's needed (e.g. BL1 to embed only EL3 variants). Change-Id: Ib86831d5450cf778ae78c9c1f7553fe91274c2fa
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Sandrine Bailleux authored
The goal of these macros is to improve code readability by providing a concise way to check whether we are running in the expected exception level. Change-Id: If9aebadfb6299a5196e9a582b442f0971d9909b1
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- 08 May, 2014 11 commits
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danh-arm authored
Ensure a console is initialized before it is used
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danh-arm authored
Preserve x19-x29 across world switch for exception handling
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Vikram Kanigiri authored
This patch moves console_init() to bl32_early_platform_setup(). It also ensures that console_init() is called in each blX_early_platform_setup() function before the console is used e.g. through a printf call in an assert() statement. Fixes ARM-software/TF-issues#127 Change-Id: I5b1f17e0152bab674d807d2a95ff3689c5d4794e
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danh-arm authored
Set processor endianness immediately after RESET v2
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Soby Mathew authored
Previously exception handlers in BL3-1, X19-X29 were not saved and restored on every SMC/trap into EL3. Instead these registers were 'saved as needed' as a side effect of the A64 ABI used by the C compiler. That approach failed when world switching but was not visible with the TSP/TSPD code because the TSP is 64-bit, did not clobber these registers when running and did not support pre-emption by normal world interrupts. These scenarios showed that the values in these registers can be passed through a world switch, which broke the normal and trusted world assumptions about these registers being preserved. The Ideal solution saves and restores these registers when a world switch occurs - but that type of implementation is more complex. So this patch always saves and restores these registers on entry and exit of EL3. Fixes ARM-software/tf-issues#141 Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
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danh-arm authored
Optimise data cache clean/invalidate operation v2
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danh-arm authored
Use MRS/MSR instructions in assembler code v2
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danh-arm authored
Replace disable_mmu with assembler version v2
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danh-arm authored
Correct usage of data and instruction barriers v2
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danh-arm authored
Remove unused 'PL011_BASE' macro
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Sandrine Bailleux authored
'PL011_BASE' macro is no longer used because the right UART base address is now directly given to the 'console_init()' function. This patch removes it. Change-Id: I94759c99602df4876291a56f9f6a75de337a65ec
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- 07 May, 2014 6 commits
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Andrew Thoelke authored
The data cache clean and invalidate operations dcsw_op_all() and dcsw_op_loius() were implemented to invoke a DSB and ISB barrier for every set/way operation. This adds a substantial performance penalty to an already expensive operation. These functions have been reworked to provide an optimised implementation derived from the code in section D3.4 of the ARMv8 ARM. The helper macro setup_dcsw_op_args has been moved and reworked alongside the implementation. Fixes ARM-software/tf-issues#146 Change-Id: Icd5df57816a83f0a842fce935320a369f7465c7f
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Andrew Thoelke authored
There are a small number of non-EL specific helper functions which are no longer used, and also some unusable helper functions for non-existant registers. This change removes all of these functions. Change-Id: Idd656cef3b59cf5c46fe2be4029d72288b649c24
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Andrew Thoelke authored
Instead of using the system register helper functions to read or write system registers, assembler coded functions should use MRS/MSR instructions. This results in faster and more compact code. This change replaces all usage of the helper functions with direct register accesses. Change-Id: I791d5f11f257010bb3e6a72c6c5ab8779f1982b3
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Andrew Thoelke authored
disable_mmu() cannot work as a C function as there is no control over data accesses generated by the compiler between disabling and cleaning the data cache. This results in reading stale data from main memory. As assembler version is provided for EL3, and a variant that also disables the instruction cache which is now used by the BL1 exception handling function. Fixes ARM-software/tf-issues#147 Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6
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Andrew Thoelke authored
The current code does not always use data and instruction barriers as required by the architecture and frequently uses barriers excessively due to their inclusion in all of the write_*() helper functions. Barriers should be used explicitly in assembler or C code when modifying processor state that requires the barriers in order to enable review of correctness of the code. This patch removes the barriers from the helper functions and introduces them as necessary elsewhere in the code. PORTING NOTE: check any port of Trusted Firmware for use of system register helper functions for reliance on the previous barrier behaviour and add explicit barriers as necessary. Fixes ARM-software/tf-issues#92 Change-Id: Ie63e187404ff10e0bdcb39292dd9066cb84c53bf
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Andrew Thoelke authored
SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and bl31_arch_setup() after data accesses have already occured on the cold and warm boot paths. This control bit must be configured immediately on CPU reset to match the endian state of the firmware (little endian). Fixes ARM-software/tf-issues#145 Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655
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- 06 May, 2014 13 commits
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danh-arm authored
Remove variables from .data section
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Dan Handley authored
Update code base to remove variables from the .data section, mainly by using const static data where possible and adding the const specifier as required. Most changes are to the IO subsystem, including the framework APIs. The FVP power management code is also affected. Delay initialization of the global static variable, next_image_type in bl31_main.c, until it is realy needed. Doing this moves the variable from the .data to the .bss section. Also review the IO interface for inconsistencies, using uintptr_t where possible instead of void *. Remove the io_handle and io_dev_handle typedefs, which were unnecessary, replacing instances with uintptr_t. Fixes ARM-software/tf-issues#107. Change-Id: I085a62197c82410b566e4698e5590063563ed304
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danh-arm authored
dh/major refactoring
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Dan Handley authored
Reduce the number of header files included from other header files as much as possible without splitting the files. Use forward declarations where possible. This allows removal of some unnecessary "#ifndef __ASSEMBLY__" statements. Also, review the .c and .S files for which header files really need including and reorder the #include statements alphabetically. Fixes ARM-software/tf-issues#31 Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
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Dan Handley authored
Add tag names to all unnamed structs in header files. This allows forward declaration of structs, which is necessary to reduce header file nesting (to be implemented in a subsequent commit). Also change the typedef names across the codebase to use the _t suffix to be more conformant with the Linux coding style. The coding style actually prefers us not to use typedefs at all but this is considered a step too far for Trusted Firmware. Also change the IO framework structs defintions to use typedef'd structs to be consistent with the rest of the codebase. Change-Id: I722b2c86fc0d92e4da3b15e5cab20373dd26786f
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Dan Handley authored
Move the PSCI global functions out of psci_private.h and into psci.h to allow the standard service to only depend on psci.h. Change-Id: I8306924a3814b46e70c1dcc12524c7aefe06eed1
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Dan Handley authored
Move the BL function prototypes out of arch.h and into the appropriate header files to allow more efficient header file inclusion. Create new BL private header files where there is no sensible existing header file. Change-Id: I45f3e10b72b5d835254a6f25a5e47cf4cfb274c3
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Dan Handley authored
Move the function prototypes from gic.h into either gic_v2.h or gic_v3.h as appropriate. Update the source files to include the correct headers. Change-Id: I368cfda175cdcbd3a68f46e2332738ec49048e19
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Dan Handley authored
Separate out the CASSERT macro out of bl_common.h into its own header to allow more efficient header inclusion. Change-Id: I291be0b6b8f9879645e839a8f0dd1ec9b3db9639
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Dan Handley authored
Remove all usage of the vpath keyword in makefiles as it was prone to mistakes. Specify the relative paths to source files instead. Also reorder source files in makefiles alphabetically. Fixes ARM-software/tf-issues#121 Change-Id: Id15f60655444bae60e0e2165259efac71a50928b
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Dan Handley authored
Make codebase consistent in its use of #include "" syntax for user includes and #include <> syntax for system includes. Fixes ARM-software/tf-issues#65 Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
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Dan Handley authored
Move the FVP power driver to a directory under the FVP platform port as this is not a generically usable driver. Change-Id: Ibc78bd88752eb3e3964336741488349ac345f4f0
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Dan Handley authored
Move almost all system include files to a logical sub-directory under ./include. The only remaining system include directories not under ./include are specific to the platform. Move the corresponding source files to match the include directory structure. Also remove pm.h as it is no longer used. Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
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