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  1. 09 Jan, 2020 7 commits
  3. 08 Jan, 2020 2 commits
  5. 07 Jan, 2020 3 commits
  7. 06 Jan, 2020 1 commit
  9. 03 Jan, 2020 3 commits
    • Alexei Fedorov's avatar
      Merge "drivers: add a driver for snoop control unit" into integration · 22d12c41
      Alexei Fedorov authored
      22d12c41
    • Vishnu Banavath's avatar
      drivers: add a driver for snoop control unit · c20c0525
      Vishnu Banavath authored 
      

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
  processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
  L2 accesses
- manage ACP accesses.

Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.

This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT

Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: default avatarVishnu Banavath <vishnu.banavath@arm.com>
      c20c0525
    • Madhukar Pappireddy's avatar
      GCC: Upgrade to version 9.2-2019.12 of toolchain · de9bf1d8
      Madhukar Pappireddy authored 
      

This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      de9bf1d8
  11. 02 Jan, 2020 4 commits
  13. 30 Dec, 2019 2 commits
  15. 29 Dec, 2019 2 commits
    • Samuel Holland's avatar
      allwinner: Remove unused include path · 252c1d1d
      Samuel Holland authored 
      
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95
      252c1d1d
    • Samuel Holland's avatar
      bl31: Split into two separate memory regions · f8578e64
      Samuel Holland authored 
      

Some platforms are extremely memory constrained and must split BL31
between multiple non-contiguous areas in SRAM. Allow the NOBITS
sections (.bss, stacks, page tables, and coherent memory) to be placed
in a separate region of RAM from the loaded firmware image.

Because the NOBITS region may be at a lower address than the rest of
BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this
region, or el3_entrypoint_common would attempt to invalidate the dcache
for the entire address space. New symbols __NOBITS_{START,END}__ are
added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the
NOBITS region is invalidated separately.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37
      f8578e64
  17. 26 Dec, 2019 2 commits
  19. 23 Dec, 2019 3 commits
  21. 20 Dec, 2019 11 commits