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  1. 30 Mar, 2017 9 commits
    • Varun Wadekar's avatar
      Tegra186: handlers to get BL31 arguments from previous bootloader · 48afb167
      Varun Wadekar authored 
      

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.

BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.

Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      48afb167
    • Varun Wadekar's avatar
      Tegra186: delete 'Video Memory Carveout' handling · 962014f5
      Varun Wadekar authored 
      

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.

Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      962014f5
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: TZRAM aperture configuration settings · 2f583f8e
      Varun Wadekar authored 
      

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.

Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2f583f8e
    • Varun Wadekar's avatar
      Tegra186: modify the return type for `plat_get_syscnt_freq()` · 512da21a
      Varun Wadekar authored 
      Commit c073fda1

 upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned
long long.

This patch modifies the return type for the Tegra186 platform.

Change-Id: Ic9e5c364b90972265576e271582a4347e5eaa6eb
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      512da21a
    • Varun Wadekar's avatar
      Tegra186: Enable ECC and Parity Protection for A02p SKUs · 1eed3838
      Varun Wadekar authored 
      

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      1eed3838
    • Varun Wadekar's avatar
      Tegra186: mce: Uncore Perfmon ARI Programming · c11e0ddf
      Varun Wadekar authored 
      

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.

To access an uncore perfmon register, CPU software writes the ARI
request registers to specify

* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).

It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.

The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.

Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c11e0ddf
    • Varun Wadekar's avatar
      Tegra186: implement `get_target_pwr_state` handler · f3a20c32
      Varun Wadekar authored 
      

This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls.

The MCE firmware controls the power state of the CPU/CLuster/System,
so we query it to get the state and act accordingly.

Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      f3a20c32
    • Varun Wadekar's avatar
      Tegra186: mce: add the mce_update_cstate_info() helper function · 87a1df73
      Varun Wadekar authored 
      

This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup the CPU context struct.

We introduced a struct to encapsulate the request parameters, that
clients can pass on to the MCE driver. The MCE driver gets the
parameters from the struct and programs the hardware accordingly.

Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      87a1df73
    • davidcunado-arm's avatar
      Merge pull request #875 from vwadekar/tegra186-platform-support-v2 · ddc1c56f
      davidcunado-arm authored 
      Tegra186 platform support v2
      ddc1c56f
  3. 29 Mar, 2017 2 commits
  5. 28 Mar, 2017 3 commits
  7. 27 Mar, 2017 5 commits
  9. 24 Mar, 2017 1 commit
  11. 23 Mar, 2017 13 commits
  13. 22 Mar, 2017 3 commits
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored 
      

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
    • Varun Wadekar's avatar
      Tegra186: memctrl_v2: restore video memory settings · ea96ac17
      Varun Wadekar authored 
      

The memory controller loses its settings when the device enters system
suspend state.

This patch adds a handler to restore the Video Memory settings in the
memory controller, which would be called after exiting the system suspend
state.

Change-Id: I1ac12426d7290ac1452983d3c9e05fabbf3327fa
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ea96ac17
    • Varun Wadekar's avatar
      Tegra186: smmu: driver for the smmu hardware block · 4122151f
      Varun Wadekar authored 
      

This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only supports saving the SMMU settings
before entering system suspend. The MC driver and the NS world
clients take care of programming their own settings.

Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4122151f
  15. 20 Mar, 2017 4 commits