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This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.

Reported by: Rohit Khanna <rokhanna@nvidia.com>

Change-Id: I556ce17a58271cc119c86fae0a4d34267f08b338
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]

Fix variable essential type doesn't match [Rule 10.3]

Added curly braces ({}) around if/while statements in order to
  make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
  [Rule 17.7]

Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

There is a possibility that once we have checked that the GPU is
in reset, some component can get still it out of reset.
This patch removes the check register macro.

Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch adds MC registers and macros to allow CPU to access
TZRAM.

Change-Id: I46da526aa760c89714f8898591981bb6cfb29237
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to
allow addition of more MMU mappings.

Change-Id: I5c758c432f5cc77299608e25ba2fd92c3822379d
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch updates t194_nvg.h to v6.1 and does not issue NVG
commands for unsupported platforms.

Change-Id: I506b594a70a3651d01a412ab79b3c8919b1d66f1
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch updates the cache ops to use system registers in
order to trigger cache flush/clean operations.

Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0
Signed-off-by: Steven Kao <skao@nvidia.com>

Introduce platform handlers to reprogram the MSS settings.

Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates the total number of CPU clusters and number
of cores per cluster, in the platform makefile.

Change-Id: I569ebc1bb794ecab09a1043511b3d936bf450428
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch corrects the TEGRA_CAR_RESET_BASE macro value to
0x20000000 from 0x200000000.

Change-Id: Iba25394ea99237df85395c39059926c5a8b26a84
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch adds masks for the TZDRAM base/size registers.

Change-Id: I5f688793be8cace28d2aa2d177a295e4faffd666
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

This patch updates the wake mask and wake time to indicate to the
mce/mts that the cpu is powering down. Wake time is set to highest
possible value and wake mask is set to zero.

Change-Id: Ic5abf15e7b98f911def6aa610d300b0668cd287e
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

T194 XUSB has support for XUSB virtualization. It will have one
physical function (PF) and four Virtual function (VF)

There were below two SIDs for XUSB until T186.
1) #define TEGRA_SID_XUSB_HOST    0x1bU
2) #define TEGRA_SID_XUSB_DEV    0x1cU

We have below four new SIDs added for VF(s)
3) #define TEGRA_SID_XUSB_VF0    0x5dU
4) #define TEGRA_SID_XUSB_VF1    0x5eU
5) #define TEGRA_SID_XUSB_VF2    0x5fU
6) #define TEGRA_SID_XUSB_VF3    0x60U

When virtualization is enabled then we have to disable SID override
and program above SIDs in below newly added SID registers in XUSB
PADCTL MMIO space. These registers are TZ protected and so need to
be done in ATF.
a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0  (0x139cU)
c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)

This change disables SID override and programs XUSB SIDs in
above registers to support both virtualization and non-virtualization.

Change-Id: I38213a72999e933c44c5392441f91034d3b47a39
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>

This patch adds proper checks for the cpu c-stats. It checks both
cpu id and stat id before sending the nvg request to ccplex.

Change-Id: I732957d1e10d6ce6cffb2c6f5963ca614aadd948
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

Need to use bitwise & instead of condition &&.

Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.

Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>

System suspend sequence involves initializing the SMMU
as a part of the system suspend exit, which is currently
not present for Tegra194 platform.

Thus call tegra_smmu_init() as a part of system suspend
exit.

Change-Id: I3086301743019e05a40fd221372e7f8713f286ae
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch updates the cpu core id calculation to match with
internal numbering method used by the MTS.

Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.

Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed-off-by: Steven Kao <skao@nvidia.com>

Fake system suspend for Tegra194, calls the routine
tegra_secure_entrypoint() instead of calling WFI.
In essence, this is a debug mode that ensures
that the code path of kernel->ATF and back to kernel
is executed without depending on other components
involved in the system suspend path.

This is for ensuring that verification of system suspend
can be done on pre-silicon platforms without depending on
the rest of the layers being enabled.

Change-Id: I18572b169b7ef786f9029600dad9ef5728634f2b
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch converts the 'target_cpu' and 'target_cluster' variables from
the tegra_soc_pwr_domain_on() handler to 32-bits. This fixes the signed
comparison warning flagged by the compiler.

Change-Id: Idfd7ad2a62749bb0dd032eb9eb5f4b28df32bba0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds platform support for the Memory Controller and
SMMU drivers, for the Tegra194 SoC.

Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support for cpu suspend in T19x soc.

Change-Id: I8ef1d3e03ee9c528dec34eaff6dcbbfa43941484
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race condition with other CPUs.

Now AARCH64 will be set with cluster on in pwr_domain_on(), and
all CPUs on this cluster will be set together. It doesn't need to
set AARCH64 again in pwr_domain_suspend(), so the race condition
can be avoided.

Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

Implement rdist save/resore functions to support low power scenarios.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7

Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.

The current memory gain is 0x6000 for fvp and 0x8000 for juno.

Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

The number of levels in the topology has not changed but the count of
processing elements on the lowest layer is now multiplied by the value
of FVP_MAX_PE_PER_CPU.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ia1568a40ea33dbbbcdfab6c8ab6d19f4db0b8eb4

This patch removes the code to enable L2 ECC parity protection
bit, as Tegra194 does not have any Cortex-A57 CPUs.

Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.

Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements the platform handler to return the pointer
to the power domain tree.

Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.

Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.

Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

- In pre-silicon platforms, MCE might not be ready
  to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
  MCE's acknowledgment to enter system suspend

Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch does the following:
1. Populate the cstate info corresponding to system suspend
   and communicate it to the MCE
2. Ask for MCE's acknowledgement for entering system suspend
   and instruct MCE to get inside system suspend once
   permitted

Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.

Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.

Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17

 because of n1sdp platform.

Now it has been verified that PIE does work for n1sdp platform also, so
enabling it again for all arm platforms.

Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM
2. Switch CLKSQ1/TDCLKSQ control to SPM
3. Switch ck_off/axi_26m control to SPM

BUG=b:136980838
TEST=system suspend/resume passed

Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18
Signed-off-by: Roger Lu <roger.lu@mediatek.com>

ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistributor frames
which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe`
function to probe all the GICR frames available in the platform.

Introduce `plat_arm_override_gicr_frames` function which platforms can
use to override the default gicr_frames which holds the GICR base
address of the primary cpu.

Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>