1. 13 Nov, 2017 2 commits
    • Jeenu Viswambharan's avatar
      GIC: Introduce API to get interrupt ID · 4ee8d0be
      Jeenu Viswambharan authored
      
      
      Acknowledging interrupt shall return a raw value from the interrupt
      controller in which the actual interrupt ID may be encoded. Add a
      platform API to extract the actual interrupt ID from the raw value
      obtained from interrupt controller.
      
      Document the new function. Also clarify the semantics of interrupt
      acknowledge.
      
      Change-Id: I818dad7be47661658b16f9807877d259eb127405
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      4ee8d0be
    • Jeenu Viswambharan's avatar
      GICv2: Fix populating PE target data · 058efeef
      Jeenu Viswambharan authored
      
      
      This patch brings in the following fixes:
      
        - The per-PE target data initialized during power up needs to be
          flushed so as to be visible to other PEs.
      
        - Setup per-PE target data for the primary PE as well. At present,
          this was only setup for secondary PEs when they were powered on.
      
      Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      058efeef
  2. 09 Nov, 2017 1 commit
  3. 06 Nov, 2017 2 commits
  4. 03 Nov, 2017 1 commit
    • Soby Mathew's avatar
      Fix PSCI STAT time stamp collection · bfc87a8d
      Soby Mathew authored
      
      
      This patch includes various fixes for PSCI STAT functionality
      relating to timestamp collection:
      
      1. The PSCI stat accounting for retention states for higher level
      power domains were done outside the locks which could lead to
      spurious values in some race conditions. This is moved inside
      the locks. Also, the call to start the stat accounting was redundant
      which is now removed.
      
      2. The timestamp wrap-around case when calculating residency did
      not cater for AArch32. This is now fixed.
      
      3. In the warm boot path, `plat_psci_stat_accounting_stop()` was
      getting invoked prior to population of target power states. This
      is now corrected.
      
      Change-Id: I851526455304fb74ff0a724f4d5318cd89e19589
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      bfc87a8d
  5. 02 Nov, 2017 1 commit
  6. 01 Nov, 2017 2 commits
  7. 26 Oct, 2017 1 commit
  8. 25 Oct, 2017 3 commits
  9. 24 Oct, 2017 2 commits
  10. 18 Oct, 2017 3 commits
  11. 17 Oct, 2017 3 commits
  12. 16 Oct, 2017 13 commits
  13. 13 Oct, 2017 2 commits
  14. 11 Oct, 2017 2 commits
    • Soby Mathew's avatar
      ARM platforms: enable GICv3 state save/restore · e35a3fb5
      Soby Mathew authored
      
      
      Provides GICv3 save/restore feature to arm_system_pwr_domain_resume and
      arm_system_pwr_domain_save functions.
      
      Introduce FVP PSCI power level 3 (System level) support. This is solely
      done to provide example code on how to use the GICv3 save and restore
      helpers.
      
      Also make CSS GICv3 platforms power off the Redistributor on SYSTEM
      SUSPEND as its state is saved and restored.
      
      Change-Id: I0d852f3af8824edee1a17c085cf593ddd33a4e77
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      Co-Authored-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      e35a3fb5
    • Soby Mathew's avatar
      ARM platforms: Add support for EL3 TZC memory region · a22dffc6
      Soby Mathew authored
      
      
      Some recent enhancements to EL3 runtime firmware like support for
      save and restoring GICv3 register context during system_suspend
      necessitates additional data memory for the firmware. This patch
      introduces support for creating a TZC secured DDR carveout for use
      by ARM reference platforms. A new linker section `el3_tzc_dram` is
      created using platform supplied linker script and data marked with
      the attribute `arm_el3_tzc_dram` will be placed in this section.
      The FVP makefile now defines the `PLAT_EXTRA_LD_SCRIPT` variable to
      allow inclusion of the platform linker script by the top level BL31
      linker script.
      
      Change-Id: I0e7f4a75a6ac51419c667875ff2677043df1585d
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      a22dffc6
  15. 05 Oct, 2017 1 commit
    • Soby Mathew's avatar
      GICv3: add functions for save and restore · ebf1ca10
      Soby Mathew authored
      
      
      During system suspend, the GICv3 Distributor and Redistributor context
      can be lost due to power gating of the system power domain. This means
      that the GICv3 context needs to be saved prior to system suspend and
      restored on wakeup. Currently the consensus is that the Firmware should
      be in charge of this. See tf-issues#464 for more details.
      
      This patch introduces helper APIs in the GICv3 driver to save and
      restore the Distributor and Redistributor contexts. The GICv3 ITS
      context is not considered in this patch because the specification says
      that the details of ITS power management is implementation-defined.
      These APIs are expected to be appropriately invoked by the platform
      layer during system suspend.
      
      Fixes ARM-software/tf-issues#464
      
      Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      ebf1ca10
  16. 04 Oct, 2017 1 commit
    • Jeenu Viswambharan's avatar
      TSP: Support multi-threading CPUs on FVP · 5e4ca661
      Jeenu Viswambharan authored
      Commit 11ad8f20
      
       added supporting
      multi-threaded CPUs on FVP platform, including modifications for
      calculating CPU IDs. This patch imports the strong definition of the
      same CPU ID calculation on FVP platform for TSP.
      
      Without this patch, TSP on FVP was using the default CPU ID calculation,
      which would end up being wrong on CPUs with multi-threading.
      
      Change-Id: If67fd492dfce1f57224c9e693988c4b0f89a9a9a
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      5e4ca661