- 10 Jul, 2020 14 commits
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Konstantin Porotchkin authored
- Fix the line address macro - LLC invalidate and enable before ways lock for allocation - Add support for limited SRAM size allocation - Add SRAM RW test function Change-Id: I1867ece3047566ddd7931bd7472e1f47fb42c8d4 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module. It is followed by 4MB of shared memory. Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Since the AP process can be enabled on different setups, the information about used comphy lane should be passed to AP FW. For instance: - A8K development board uses comphy lane 2 for eth 0 - cn913x development board uses comphy lane 4 for eth 0 Change-Id: Icf001fb3eea4d9c24c09384e49844ecaf8655ad2 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Now when mg_conf_cm3 driver is present - move all relevant code there. Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
After configuring comphy to AP mode also start AP FW. Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Grzegorz Jaszczyk authored
Implement function which will allow to start AP FW. Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Konstantin Porotchkin authored
Change the binary image alignment from 4 to 16. The PKCS signature verification fails for unaligned images. Change-Id: Ieb08dc3ea128790f542ad93e3c948117567a65af Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Replace deprecated mbedtls_sha256 with mbedtls_sha256_ret The mbedtls_pk_parse_key does not work correctly anymore with the DER buffer embedded in the secure image extentson using the buffer size as the the key length. Move to mbedtls_pk_parse_subpubkey API that handles such case correctly. The DER format already contains the key length, so there is no particular reason to supply it to the key parser. Update the doimage version to 3.3 Change-Id: I0ec5ee84b7d1505b43138e0b7a6bdba44a6702b6 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Sandrine Bailleux authored
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Manish V Badarkhe authored
Included cot_descriptors.dtsi in platform device tree (fvp_tb_fw_config.dts). Also, updated the maximum size of tb_fw_config to 0x1800 in order to accomodate the device tree for CoT descriptors. Follow up patch will parse the device tree for these CoT descriptors and fill the CoT descriptor structures at runtime instead of using static CoT descriptor structures in the code base. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I90122bc713f6842b82fb019b04caf42629b4f45a
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Sandrine Bailleux authored
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Manish V Badarkhe authored
Added CoT descriptor nodes and properties in device tree. Currently, CoT descriptors which are used by BL2 are added as part of device tree. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0
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Sandrine Bailleux authored
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- 09 Jul, 2020 3 commits
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Manish V Badarkhe authored
Added a build option 'COT_DESC_IN_DTB' to create chain of trust at runtime using fconf. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89
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Sandrine Bailleux authored
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Manish V Badarkhe authored
Updated the CoT binding document to show chain of trust relationship with the help of 'authentication method' and 'authentication data' instead of showing content of certificate and fixed rendering issue while creating html page using this document. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b
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- 08 Jul, 2020 1 commit
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Sandrine Bailleux authored
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- 07 Jul, 2020 3 commits
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André Przywara authored
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Varun Wadekar authored
This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600() helper function. This helps platforms supporting this version of the GIC600 interrupt controller to function with the generic GIC driver. Verified with tftf-validation test suite ******************************* Summary ******************************* > Test suite 'Framework Validation' Passed > Test suite 'Timer framework Validation' Passed ================================= Tests Skipped : 0 Tests Passed : 6 Tests Failed : 0 Tests Crashed : 0 Total tests : 6 ================================= NOTICE: Exiting tests. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574
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Manish Pandey authored
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- 06 Jul, 2020 1 commit
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Abdellatif El Khlifi authored
This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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- 02 Jul, 2020 4 commits
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Madhukar Pappireddy authored
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Mark Dykes authored
* changes: stm32mp1: shared resources: apply registered configuration stm32mp1: shared resources: count GPIOZ bank pins stm32mp1: shared resources: define resource identifiers
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Mark Dykes authored
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Manish Pandey authored
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- 01 Jul, 2020 3 commits
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Lauren Wehrmeister authored
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Lauren Wehrmeister authored
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Sandrine Bailleux authored
Fix all external broken links reported by Sphinx linkcheck tool. This does not take care of broken cross-references between internal TF-A documentation files. These will be fixed in a future patch. Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 30 Jun, 2020 3 commits
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Manish Pandey authored
There were some links in the file "ras.rst" which were broken, this patch fixes all the broken links in this file. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d
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Sandrine Bailleux authored
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Sandrine Bailleux authored
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- 29 Jun, 2020 8 commits
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Manish Pandey authored
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Sami Mujawar authored
The TF-A firmware build system is capable of building on both Unix like and Windows host PCs. The commit ID 7ff088 "Enable MTE support" updated the Makefile to conditionally enable the MTE support if the AArch64 architecture revision was greater than 8.5. However, the Makefile changes were dependent on shell commands that are only available on unix shells, resulting in build failures on a Windows host PC. This patch fixes the Makefile by using a more portable approach for comparing the architecture revision. Change-Id: Icb56cbecd8af5b0b9056d105970ff4a6edd1755a Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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Mark Dykes authored
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Mark Dykes authored
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Manish V Badarkhe authored
Added assert in the code to check valid address of dtb information structure retrieved from fw_config device tree. This patch fixes coverity defect:360213. Also, removed conditional calling of "fconf_populate" as "fconf_populate" function already checks the validity of the device tree address received and go to panic in case of address is NULL. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib83e4e84a95e2456a12c7a2bb3fe70461d882cba
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André Przywara authored
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Samuel Holland authored
The non-secure world has no business accessing the CPU power switches in the PRCM; those are handled by TF-A or the SCP. Only allow access to the clock control part of the PRCM. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I657b97f4ea8a0073448ad3343fbc66ba168ed89e
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Masahiro Yamada authored
The .rela.dyn section is the same for BL2-AT-EL3, BL31, TSP. Move it to the common header file. I slightly changed the definition so that we can do "RELA_SECTION >RAM". It still produced equivalent elf images. Please note I got rid of '.' from the VMA field. Otherwise, if the end of previous .data section is not 8-byte aligned, it fails to link. aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes aarch64-linux-gnu-ld.bfd: warning: changing start of section .rela.dyn by 4 bytes make: *** [Makefile:1071: build/qemu/release/bl31/bl31.elf] Error 1 Change-Id: Iba7422d99c0374d4d9e97e6fd47bae129dba5cc9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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