- 20 Aug, 2020 1 commit
-
-
Sandrine Bailleux authored
Change-Id: I5362780db422772fd547dc8e68e459109edccdd0 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
- 18 Aug, 2020 2 commits
-
-
Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
-
Manish V Badarkhe authored
Documented the CPU specific build macros created for AT speculative workaround. Updated the description of 'ERRATA_SPECULATIVE_AT' errata workaround option. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie46a80d4e8183c1d5c8b153f08742a04d41a2af2
-
- 17 Aug, 2020 1 commit
-
-
Madhukar Pappireddy authored
SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_VE_USE_SP804_TIMER. This patch removes platform specific build flag and adds generic flag `USE_SP804_TIMER` to be set to 1 by platform if needed. Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
-
- 14 Aug, 2020 4 commits
-
-
Sandrine Bailleux authored
Ensuring that each file changed by a patch has the correct copyright and license information does not only apply to documentation files but to all files within the source tree. Move the guidance for copyright and license headers out of the paragraph about updating the documentation to avoid any confusion. Also do some cosmetic changes (adding empty lines, fitting in longer lines in the 80-column limit, ...) to improve the readability of the RST file. Change-Id: I241a2089ca9db70f5a9f26b7070b947674b43265 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
Sandrine Bailleux authored
Change-Id: Ib4ad853ebb6e28adcf9ed14714d43799f9370343 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
Sandrine Bailleux authored
Change-Id: I43e452c9993a8608b20ec029562982f5dcf8e6b2 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
Sandrine Bailleux authored
We have noticed that Phabricator (the ticketing system on tf.org [1]) has far less visibility within the community than the mailing list [2]. For this reason, let's drop usage of Phabricator for anything else than bug reports. For the rest, advise contributors to start a discussion on the mailing list, where they are more likely to get feedback. [1] https://developer.trustedfirmware.org/project/board/1/ [2] https://lists.trustedfirmware.org/mailman/listinfo/tf-a Change-Id: I7d2d3d305ad0a0f8aacc2a2f25eb5ff429853a3f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
- 10 Aug, 2020 2 commits
-
-
Alexei Fedorov authored
This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
Saurabh Gorecha authored
Adding support for QTI CHIP SC7180 on ATF Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
-
- 06 Aug, 2020 1 commit
-
-
Madhukar Pappireddy authored
Change-Id: If82aaba9f2a5a74cfb5e4381f968166037a70037 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
-
- 04 Aug, 2020 1 commit
-
-
Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
-
- 03 Aug, 2020 1 commit
-
-
Madhukar Pappireddy authored
These broken links were found with the help of this command: $> sphinx-build -M linkcheck . build A sample broken link is reported as follows: (line 80) -local- firmware-design.rst#secure-el1-payloads-and-dispatchers Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
-
- 31 Jul, 2020 1 commit
-
-
Nina Wu authored
- Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
-
- 30 Jul, 2020 5 commits
-
-
Olivier Deprez authored
Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
-
Manish V Badarkhe authored
Openssl directory path is hardcoded to '/usr' in the makefile of certificate generation and firmware encryption tool using 'OPENSSL_DIR' variable. Hence changes are done to make 'OPENSSL_DIR' variable as a build option so that user can provide openssl directory path while building the certificate generation and firmware encryption tool. Also, updated the document for this newly created build option Change-Id: Ib1538370d2c59263417f5db3746d1087ee1c1339 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
-
Grzegorz Jaszczyk authored
The purpose of rx_training had changed after last update. Currently it is not supposed to help with providing static parameters for porting layer. Instead, it aims to suit the parameters per connection. Change-Id: I2a146b71e2e20bd264c090a9a627d0b6bc56e052 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Grzegorz Jaszczyk authored
Change-Id: I0cebbaa900aa518700f13cbf02f8a97e0c76b21c Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
-
Konstantin Porotchkin authored
Add references to the OcteonTX2 CN913x family. Change-Id: I172a8e3d061086bf4843acad014c113c80359e01 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
- 28 Jul, 2020 1 commit
-
-
johpow01 authored
The link to the exception handling framework page on the System Design / Firmware Design / Section 4.3 just links to itself, so I changed it to link to the exception handling framework component document. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1
-
- 26 Jul, 2020 1 commit
-
-
Manish V Badarkhe authored
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to be not correct for the platform which doesn't implement soc-id functionality i.e. functions to retrieve both soc-version and soc-revision. Hence introduced a platform function which will check whether SMCCC feature is available for the platform. Also, updated porting guide for the newly added platform function. Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
-
- 23 Jul, 2020 1 commit
-
-
johpow01 authored
This reverts commit 11af40b6, reversing changes made to 2afcf1d4. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
-
- 22 Jul, 2020 2 commits
-
-
Vijayenthiran Subramaniam authored
Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual Platforms. Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
-
Alexei Fedorov authored
This patch adds support for Measured Boot functionality to FVP platform code. It also defines new properties in 'tpm_event_log' node to store Event Log address and it size 'tpm_event_log_sm_addr' 'tpm_event_log_addr' 'tpm_event_log_size' in 'event_log.dtsi' included in 'fvp_tsp_fw_config.dts' and 'fvp_nt_fw_config.dts'. The node and its properties are described in binding document 'docs\components\measured_boot\event_log.rst'. Change-Id: I087e1423afcb269d6cfe79c1af9c348931991292 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
- 21 Jul, 2020 4 commits
-
-
Javier Almansa Sobrino authored
definitions Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I1c5cc8af34c02a6294ffc44a26152fb8984927fc
-
Olivier Deprez authored
Former EL3 Secure Partition Manager using MM protocol is renamed Secure Partition Manager (MM). A new Secure Partition Manager document covers TF-A support for the PSA FF-A compliant implementation. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I9763359c2e96181e1726c8ad72738de293b80eb4
-
Javier Almansa Sobrino authored
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Ib327bda239bb5163c60764bae90b0739589dcf66
-
Alexei Fedorov authored
This patch adds the following models FVP_Base_Neoverse-E1x1 FVP_Base_Neoverse-E1x2 FVP_Base_Neoverse-E1x4 to the list of supported FVP platforms. Change-Id: Ib526a2a735f17724af3a874b06bf69b4ca85d0dd Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
- 17 Jul, 2020 1 commit
-
-
Leonardo Sandoval authored
docker (container) is another way to build the documentation and fortunately there is already a docker image (sphinxdoc/sphinx) with sphinx so we can use it to generate the documentation. Change-Id: I06b0621cd7509a8279655e828680b92241b9fde4 Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
-
- 10 Jul, 2020 3 commits
-
-
Javier Almansa Sobrino authored
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I6d3949a971fada5a086b788dbe274f8451fcfc0d
-
Konstantin Porotchkin authored
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Jacky Bai authored
The i.MX 8MP Media Applications Processor is part of the growing i.MX8M family targeting the consumer and industrial market. It brings an effective Machine Learning and AI accelerator that enables a new class of applications. It is built in 14LPP to achieve both high performance and low power consumption and relies on a powerful fully coherent core complex based on a quad core Arm Cortex-A53 cluster and Cortex-M7 low-power coprocessor, audio digital signal processor, machine learning and graphics accelerators. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a
-
- 09 Jul, 2020 2 commits
-
-
Manish V Badarkhe authored
Added a build option 'COT_DESC_IN_DTB' to create chain of trust at runtime using fconf. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89
-
Manish V Badarkhe authored
Updated the CoT binding document to show chain of trust relationship with the help of 'authentication method' and 'authentication data' instead of showing content of certificate and fixed rendering issue while creating html page using this document. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b
-
- 04 Jul, 2020 3 commits
-
-
Masahiro Yamada authored
Fix the version inconsistency in the same file. I tested QEMU 5.0.0, and it worked for me. Change-Id: I9d8ca9aae1e413410eb5676927e13ae4aee9fad8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-
Masahiro Yamada authored
In my understanding, /dev/vda2 does not exist unless you add virtio drive to the qemu command line. The rootfs is already specified by '-initrd rootfs.cpio.gz'. Change-Id: Ifdca5d4f3819d87ef7e8a08ed870872d24b86370 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-
Masahiro Yamada authored
This commit solves the limitation, "No build instructions for QEMU_EFI.fd and rootfs-arm64.cpio.gz" Document the steps to build them. Change-Id: Ic6d895617cf71fe969f4aa9820dad25cc6182023 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-
- 01 Jul, 2020 1 commit
-
-
Sandrine Bailleux authored
Fix all external broken links reported by Sphinx linkcheck tool. This does not take care of broken cross-references between internal TF-A documentation files. These will be fixed in a future patch. Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
-
- 30 Jun, 2020 1 commit
-
-
Manish Pandey authored
There were some links in the file "ras.rst" which were broken, this patch fixes all the broken links in this file. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I00cf080e9338af5786239a4843cb4c2e0cc9d99d
-
- 26 Jun, 2020 1 commit
-
-
Manish V Badarkhe authored
Updated the porting guide for the usage of received arguments in BL2 and BL32 setup functions in case of Arm platform. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ia83a5607fed999819d25e49322b3bfb5db9425c0
-