Skip to content

GitLab

Switch branch/tag
  1. 27 Feb, 2018 1 commit
  3. 30 Jan, 2018 1 commit
    • Caesar Wang's avatar
      rockchip/rk3399: Fix memory corruptions or illegal memory access · de3c3007
      Caesar Wang authored 
      

Coverity scan done for the coreboot project found the issue:
Coverity (*** CID 1385418: Memory - illegal accesses (OVERRUN))
Coverity (*** CID 1385419: Memory - corruptions  (OVERRUN))

Fix the Converity error issue with store_cru[] loop needs to be one
element bigger.

Fixes: ARM-software/tf-issues#544

Change-Id: I420f0a660b24baaa5fc5e78fca242cf750c9bbc7
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      de3c3007
  5. 24 Jan, 2018 4 commits
  7. 19 Jan, 2018 2 commits
    • Julius Werner's avatar
      rockchip: Move to MULTI_CONSOLE_API · 890abc33
      Julius Werner authored 
      

This patch changes all Rockchip platforms to use the new
MULTI_CONSOLE_API. The platform-specific plat_crash_console
implementations are removed so that the platform can use the ones from
the common platform code instead.

Also change the registers used in plat_crash_print_regs. The existing
use of x16 and x17 has always been illegal, since those registers are
reserved for use by the linker as a temporary scratch registers in
intra-procedure-call veneers and can never be expected to maintain their
values across a function call.

Change-Id: I8249424150be8d5543ed4af93b56756795a5288f
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      890abc33
    • Julius Werner's avatar
      rockchip: Use coreboot-supplied serial console on coreboot systems · 3c250b9a
      Julius Werner authored 
      

This patch changes all Rockchip platforms to initialize the serial
console with information supplied by coreboot rather than hardcoded
base address and divisor values if BL31 is run on top of coreboot.
Moving the BL2-to-BL31 parameter parsing as early as possible to ensure
that the console is available for all following code.

Also update the Rockchip platform to use MULTI_CONSOLE_API.

Change-Id: I670d350fa2f8b8133539f91ac14977ab47db60d9
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      3c250b9a
  9. 02 Dec, 2017 1 commit
  11. 30 Nov, 2017 1 commit
    • David Cunado's avatar
      Do not enable SVE on pre-v8.2 platforms · 3872fc2d
      David Cunado authored 
      

Pre-v8.2 platforms such as the Juno platform does not have
the Scalable Vector Extensions implemented and so the build
option ENABLE_SVE is set to zero.

This has a minor performance improvement with no functional
impact.

Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1
Signed-off-by: default avatarDavid Cunado <david.cunado@arm.com>
      3872fc2d
  13. 29 Nov, 2017 1 commit
    • Antonio Nino Diaz's avatar
      Replace magic numbers in linkerscripts by PAGE_SIZE · a2aedac2
      Antonio Nino Diaz authored 
      

When defining different sections in linker scripts it is needed to align
them to multiples of the page size. In most linker scripts this is done
by aligning to the hardcoded value 4096 instead of PAGE_SIZE.

This may be confusing when taking a look at all the codebase, as 4096
is used in some parts that aren't meant to be a multiple of the page
size.

Change-Id: I36c6f461c7782437a58d13d37ec8b822a1663ec1
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      a2aedac2
  15. 06 Nov, 2017 1 commit
  17. 29 Aug, 2017 7 commits
  19. 14 Jul, 2017 1 commit
  21. 05 Jul, 2017 1 commit
  23. 30 Jun, 2017 1 commit
    • Caesar Wang's avatar
      rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume · c3710ee7
      Caesar Wang authored 
      

This patch fixes the two things as follows:

1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash".

2) fixes the warnings log.
We always hit the warnings thing during the suspend, as below log:
..
[   51.022334] CPU5: shutdown
[   51.025069] psci: CPU5 killed.
INFO:    sdram_params->ddr_freq = 928000000
WARNING: rk3399_flash_l2_b:reg 28830380,wait

When the L2 completes the clean and invalidate sequence, it asserts the
L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then
the L2 deasserts L2FLUSHDONE.

Then, a loop without a delay isn't really great to measure time. We should
probably add a udelay(10) or so in there and then maybe replace the WARN()
after the loop. In the actual tests, the L2 cache will take ~4ms by
default for big cluster.

In the real world that give 10ms for the enough margin, like the
ddr/cpu/cci frequency and other factors that will affect it.

Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      c3710ee7
  25. 28 Jun, 2017 1 commit
    • Caesar Wang's avatar
      rockchip: enable A53's erratum 855873 for rk3399 · dea1e8ee
      Caesar Wang authored 
      

For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't
support WriteEvict. and you will hit the condition L2ACTLR[3] with 0,
as the Evict transactions should propagate to CCI-500 since it has
snoop filters.

Maybe this erratum applies to all Cortex-A53 cores so far, especially
if RK3399's A53 is a r0p4. we should enable it to avoid data corruption,

Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      dea1e8ee
  27. 26 Jun, 2017 1 commit
  29. 08 Jun, 2017 10 commits
  31. 03 May, 2017 1 commit
  33. 07 Apr, 2017 1 commit
  35. 20 Mar, 2017 1 commit
  37. 01 Mar, 2017 1 commit
  39. 24 Feb, 2017 2 commits