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  1. 11 Oct, 2020 1 commit
  3. 04 Oct, 2020 1 commit
  5. 02 Oct, 2020 2 commits
  7. 29 Sep, 2020 1 commit
  9. 28 Sep, 2020 1 commit
  11. 18 Aug, 2020 1 commit
  13. 17 Aug, 2020 1 commit
  15. 10 Aug, 2020 1 commit
  17. 03 Aug, 2020 1 commit
  19. 31 Jul, 2020 1 commit
  21. 30 Jul, 2020 4 commits
  23. 22 Jul, 2020 1 commit
  25. 21 Jul, 2020 1 commit
  27. 10 Jul, 2020 2 commits
    • Konstantin Porotchkin's avatar
      plat: marvell: armada: a8k: change CCU LLC SRAM mapping · 0a977b9b
      Konstantin Porotchkin authored 
      

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      0a977b9b
    • Jacky Bai's avatar
      plat: imx8mp: Add the basic support for i.MX8MP · a775ef25
      Jacky Bai authored 
      

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a
      a775ef25
  29. 04 Jul, 2020 3 commits
  31. 01 Jul, 2020 1 commit
  33. 19 Jun, 2020 1 commit
  35. 09 Jun, 2020 1 commit
    • Andre Przywara's avatar
      GICv3: GIC-600: Detect GIC-600 at runtime · b4ad365a
      Andre Przywara authored 
      

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      b4ad365a
  37. 06 Jun, 2020 2 commits
  39. 27 May, 2020 1 commit
    • Usama Arif's avatar
      plat/arm: Introduce TC0 platform · f5c58af6
      Usama Arif authored 
      

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: default avatarUsama Arif <usama.arif@arm.com>
      f5c58af6
  41. 22 May, 2020 1 commit
  43. 15 Apr, 2020 2 commits
  45. 03 Apr, 2020 1 commit
  47. 31 Mar, 2020 1 commit
  49. 14 Mar, 2020 1 commit
  51. 09 Mar, 2020 1 commit
  53. 27 Feb, 2020 1 commit
  55. 26 Feb, 2020 1 commit
  57. 18 Feb, 2020 1 commit
    • Alexei Fedorov's avatar
      FVP: Fix BL31 load address and image size for RESET_TO_BL31=1 · 6227cca9
      Alexei Fedorov authored 
      

When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except for the memory reserved for Shared RAM at the start
of Trusted SRAM.
This patch fixes FVP BL31 load address and its image size for
RESET_TO_BL31=1 option. BL31 startup address should be set to
0x400_1000 and its maximum image size to the size of Trusted SRAM
minus the first 4KB of shared memory.
Loading BL31 at 0x0402_0000 as it is currently stated in
'\docs\plat\arm\fvp\index.rst' causes EL3 exception when the
image size gets increased (i.e. building with LOG_LEVEL=50)
but doesn't exceed 0x3B000 not causing build error.

Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      6227cca9
  59. 07 Feb, 2020 1 commit
    • Vijayenthiran Subramaniam's avatar
      plat/arm/sgi: introduce number of chips macro · 4d37aa76
      Vijayenthiran Subramaniam authored 
      

Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this flag is set to 1 and does not affect the existing single
chip platforms.

For multi-chip platforms, override the default value of
CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
platform. As an example, the command below sets the number of chiplets
to two on the RD-N1-Edge multi-chip platform:

export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all

Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
Signed-off-by: default avatarVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
      4d37aa76
  61. 06 Feb, 2020 1 commit
    • Max Shvetsov's avatar
      Adds option to read ROTPK from registers for FVP · a6ffddec
      Max Shvetsov authored 
      

Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
In case of ROT_KEY specified - generates a new hash and replaces the
original.

Note: Juno board was tested by original feature author and was not tested
for this patch since we don't have access to the private key. Juno
implementation was moved to board-specific file without changing
functionality. It is not known whether byte-swapping is still needed
for this platform.

Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
      a6ffddec