- 22 Nov, 2017 1 commit
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Leo Yan authored
Set alignment size to 512B so finally we can get fip.bin with 512B alignment. This can avoid stuck issue for 'fastboot' downloading if USB driver uses DMA for data transferring. Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 01 Nov, 2017 1 commit
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Roberto Vargas authored
These macros are only defined for corresponding image, and they are undefined for other images. It means that we have to use ifdef or defined() instead of relying on being 0 by default. Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 18 Oct, 2017 2 commits
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Haojian Zhuang authored
Make RTC out of reset mode since it may be used in UEFI. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Init EDMA controller with non secure mode. A lot of peripherals are depend on EDMA controller. But EDMA controller is in secure mode by default. And this operation has to be executed in secure mode. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 13 Sep, 2017 2 commits
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Victor Chong authored
Otherwise, BL2 tries to load a BL32 image and triggers assert(result == 0) in plat_get_image_source() in hikey{960}_io_storage.c in a debug build, or displays ERROR: BL2: Failed to load image in a release build. Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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- 07 Sep, 2017 1 commit
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Leo Yan authored
Every CPU has its own debug module and this module is used by JTAG debugging and coresight tracing. If without enabling it, it's easily to introduce lockup issue when we enable debugging features. This patch is to enable CPU debug module when power on CPU; this allows connecting to all cores through JTAG and used by kernel coresight driver. Signed-off-by: Matthias Welwarsky <maw@sysgo.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 01 Sep, 2017 2 commits
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 29 Aug, 2017 2 commits
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Eleanor Bonnici authored
Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register. Since ACTLR and ACTRL_EL1 are different registers this patch renames these constants for clarity. Change-Id: I2a9e402dab7b0fcb6e481ee0d8a11eda943ed299 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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Leo Yan authored
At the system boot time we need enable watchdog reset, otherwise after the watchdog is timeout it cannot reset the SoC. We need set the bit 0 and bit 16 together, the bit 16 is mask bit so after set bit 16 we have permission to operate bit 0 and bit 0 is watchdog reset enabling bit. Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 15 Aug, 2017 1 commit
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Julius Werner authored
Assembler programmers are used to being able to define functions with a specific aligment with a pattern like this: .align X myfunction: However, this pattern is subtly broken when instead of a direct label like 'myfunction:', you use the 'func myfunction' macro that's standard in Trusted Firmware. Since the func macro declares a new section for the function, the .align directive written above it actually applies to the *previous* section in the assembly file, and the function it was supposed to apply to is linked with default alignment. An extreme case can be seen in Rockchip's plat_helpers.S which contains this code: [...] endfunc plat_crash_console_putc .align 16 func platform_cpu_warmboot [...] This assembles into the following plat_helpers.o: Sections: Idx Name Size [...] Algn 9 .text.plat_crash_console_putc 00010000 [...] 2**16 10 .text.platform_cpu_warmboot 00000080 [...] 2**3 As can be seen, the *previous* function actually got the alignment constraint, and it is also 64KB big even though it contains only two instructions, because the .align directive at the end of its section forces the assembler to insert a giant sled of NOPs. The function we actually wanted to align has the default constraint. This code only works at all because the linker just happens to put the two functions right behind each other when linking the final image, and since the end of plat_crash_console_putc is aligned the start of platform_cpu_warmboot will also be. But it still wastes almost 64KB of image space unnecessarily, and it will break under certain circumstances (e.g. if the plat_crash_console_putc function becomes unused and its section gets garbage-collected out). There's no real way to fix this with the existing func macro. Code like func myfunc .align X happens to do the right thing, but is still not really correct code (because the function label is inserted before the .align directive, so the assembler is technically allowed to insert padding at the beginning of the function which would then get executed as instructions if the function was called). Therefore, this patch adds a new parameter with a default value to the func macro that allows overriding its alignment. Also fix up all existing instances of this dangerous antipattern. Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 26 Jul, 2017 1 commit
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Leo Yan authored
After disconnect Jumper pin 1-2 in J15 header, the signal VBUS_DET is to be pulled down to low level. This will assert the interrupt signal in PMIC and trigger IRQ in GIC; the asserted signal from VBUS_DET is level triggered and kernel reports the warning for unhooked interrupt handling; and VBUS_DET stays with low level, this triggers IRQ storm in kernel. This patch is to disable interrupt for VBUS_DET in PMIC, this can dismiss the verbose log and IRQ storm after kernel booting. [ 40.835279] irq 57: nobody cared (try booting with the "irqpoll" option) [ 40.842075] CPU: 0 PID: 980 Comm: irq/57-hi655x-p Not tainted 4.4.77-568944-g576a0114dec8-dirty #667 [ 40.851303] Hardware name: HiKey Development Board (DT) [ 40.856580] Call trace: [ 40.859060] [<ffffff800808c4cc>] dump_backtrace+0x0/0x1e0 [ 40.864516] [<ffffff800808c8ac>] show_stack+0x20/0x28 [ 40.869622] [<ffffff80084b9688>] dump_stack+0xa8/0xe0 [ 40.874729] [<ffffff800812dd5c>] __report_bad_irq+0x40/0xec [ 40.880360] [<ffffff800812e0bc>] note_interrupt+0x1e4/0x2d8 [ 40.885992] [<ffffff800812b11c>] handle_irq_event_percpu+0xd8/0x268 [ 40.892324] [<ffffff800812b2f8>] handle_irq_event+0x4c/0x7c [ 40.897955] [<ffffff800812ecbc>] handle_level_irq+0xcc/0x178 [ 40.903672] [<ffffff800812a778>] generic_handle_irq+0x34/0x4c [ 40.909481] [<ffffff80085074c8>] pl061_irq_handler+0xa8/0x124 [ 40.915286] [<ffffff800812a778>] generic_handle_irq+0x34/0x4c [ 40.921092] [<ffffff800812a820>] __handle_domain_irq+0x90/0xf8 [ 40.926985] [<ffffff8008082620>] gic_handle_irq+0x58/0xa8 Signed-off-by: Dmitry Shmidt <dimitrysh@google.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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- 14 Jul, 2017 1 commit
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 12 Jul, 2017 3 commits
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
PLATFORM_LINKER_FORMAT and PLATFORM_LINKER_ARCH defines are removed from plat/hisilicon/hikey/include/platform_def.h since there are already defined in include/plat/common/common_def.h which is included by plat/hisilicon/hikey/hikey_def.h which is included by plat/hisilicon/hikey/include/platform_def.h The line $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) is removed from plat/hisilicon/hikey/platform.mk to clear the warning below: Makefile:544: warning: overriding commands for target `check_SCP_BL2' plat/hisilicon/hikey/platform.mk:19: warning: ignoring old commands for target `check_SCP_BL2' $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) already exists in Makefile and applies to plat hikey so is redundant in plat/hisilicon/hikey/platform.mk Signed-off-by: Victor Chong <victor.chong@linaro.org>
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Victor Chong authored
Signed-off-by: Victor Chong <victor.chong@linaro.org>
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- 10 Jul, 2017 1 commit
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Haojian Zhuang authored
Fix cortex a53 errata issues: #836870, #843419, #855873. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 14 Jun, 2017 1 commit
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Varun Wadekar authored
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 07 Jun, 2017 1 commit
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Vincent Guittot authored
enable PMF service call and instrumetion for hikey platform Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
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- 31 May, 2017 4 commits
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Leo Yan authored
This patch is to enable CPU suspend/resume and system level's suspend/resume; also enable system power off state. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Leo Yan authored
The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port for cluster 0 in BL31 platform setup flow. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Leo Yan authored
Fix for CPU topology so present the CPU core numbers for two clusters; Base on this fixing, the PSCI can maintain correct power states. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Fix uninitliazed variable in ddr driver code. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 24 May, 2017 3 commits
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Haojian Zhuang authored
Support BL31 and PSCI. Enable multiple cores in PSCI. Change-Id: I66c39e1e9c4c45ac41a0142ed2070d79a3ac5ba3 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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Haojian Zhuang authored
BL2 is used to load BL31 and SCP_BL2. In HiKey platform, SCP_BL2 is the mcu firmware that is used to scale cpu frequency and switch low power mode. Change-Id: I1621aa65bea989fd125ee8502fd56ef72362bf97 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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Haojian Zhuang authored
Initialize regulators, pins and eMMC in BL1. Only SRAM could be used in BL1. So BL2 will be loaded from eMMC into SRAM later. Change-Id: I8e7ef82ffa29a3c647c9d2d2981e8759ee85d833 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
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