- 07 Feb, 2019 8 commits
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Varun Wadekar authored
This patch introduces explicit linker variables to mark the start and end of the per-cpu bakery lock section to help bakery_lock_normal.c calculate the size of the section. This patch removes the previously used '__PERCPU_BAKERY_LOCK_SIZE__' linker variable to make the code uniform across GNU linker and ARM linker. Change-Id: Ie0c51702cbc0fe8a2076005344a1fcebb48e7cca Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch includes bl_common.h from plat_trampoline.S to link with the __BL31_END__ symbol. Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch modfies the 'tegra_soc_pwr_domain_power_down_wfi' handler to use BL31_BASE variable, provided by bl_common.h Change-Id: I9747228d0193c1ae6999284458b9f866955a61a2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch includes bl_common.h to get access to the linker defined symbols. Change-Id: I9aa4a6e730273d75a53438854f69971e485bc904 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes the unused functions that are marked as .global in code but not defined anywhere in the code. Change-Id: Ia5057a77c0b0b4a61043eab868734cd3437304cc Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch modifies the code to turn __1printf and __2printf into proper functions to fix the following errors flagged by armlink. Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf. Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf. Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf. Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf. Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf. Error: L6318W: backtrace.o(.text.backtrace) contains branch to a non-code symbol __2printf. Change-Id: I89126bc2b9db44ce8b8fc9fb1e3fc4c8c60c47a4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch stops including common_def.h from platform_def.h to fix a circular depoendency between them. This means platform_def.h now has to define the linker macros: * PLATFORM_LINKER_FORMAT * PLATFORM_LINKER_ARCH Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Kalyani Chidambaram authored
The scatterfile to support armlink, does not seem to support shift operator. To handle this define CACHE_WRITEBACK_GRANULE with the direct value. Change-Id: I19afc7cb9c55a08cb0703f284d91018d3214353f Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
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- 06 Feb, 2019 3 commits
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Antonio Niño Díaz authored
Tf2.0 tegra downstream rebase 1.25.19
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Antonio Niño Díaz authored
drivers: generic_delay_timer: Assert presence of Generic Timer
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Antonio Nino Diaz authored
The Generic Timer is an optional extension to an ARMv7-A implementation. The generic delay timer can be used from any architecture supported by the Trusted Firmware. In ARMv7 it is needed to check that this feature is present. In ARMv8 it is always present. Change-Id: Ib7e8ec13ffbb2f64445d4ee48ed00f26e34b79b7 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 05 Feb, 2019 11 commits
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Varun Wadekar authored
This patch adds information about the Tegra186 platforms to the docs. Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes this macro and its usage as it is used only within the Tegra186 files and all derived platforms keep the macro enabled. Change-Id: Ib831b3c002ba4dedc3d5fafbb7d321daa28fa9ea Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch dynamically maps the first page of trusty's code memory, before accessing it to find out if we are running a 32-bit or 64-bit image. On Tegra platforms, this means we have to increase the mappings to accomodate the new memmap entry. Change-Id: If370d1e6cfcccd69b260134c1b462d8d17bee03d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch initilises the per-CPU GIC bits during cold boot and secondary CPU power up. Commit 80c50eea accidentally left out this part. Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch udpates the SPE console driver to prepend '\r' to '\n'. This fixes the alignment of prints seen by the host machines on their UART ports. Tested by collecting the logs from host PC using Cutecom Reported by: Mustafa Bilgen <mbilgen@nvidia.com> Change-Id: I6e0b412bd71ff5eb889582071df8c157da5175ed Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Vignesh Radhakrishnan authored
As per ARM ARM D1.17.2, any physical IRQ interrupt received by the PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1', irrespective of the value of the PSTATE.I bit value. This patch programs the SCR_EL3.IRQ bit before entering CPU standby state, to allow an IRQ to wake the PE. On waking up, the previous SCR_EL3 value is restored. Change-Id: Ie81cf3a7668f5ac35f4bf2ecc461b91b9b60650c Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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Anthony Zhou authored
This patch redefines the variable LIBC_SRCS for Tegra platforms, to remove unused libc files from the list. This patch is a building block to eventually use other libc implementations in the future. Change-Id: Iccde5a75f5e2d6f4e2dbc6274beb423b80e846fd Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch introduces a build option 'OVERRIDE_LIBC' that platforms can set to override libc from the BL image. The default value is '0' to keep the library. Change-Id: I10a0b247f6a782eeea4a0359e30a8d79b1e9e4e1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Antonio Niño Díaz authored
Minor cleanup
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Antonio Niño Díaz authored
sgi/sgm: add a second maintainer for Arm's SGI and SGM platforms
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Thomas Abraham authored
Add a second maintainer for Arm's SGI and SGM platform support in trusted firmware to handle the review and maintenance of existing and upcoming platforms. Change-Id: Ie7fa8da280d9351f7543122fb261d6ac6c7e15ad Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
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- 04 Feb, 2019 6 commits
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Antonio Niño Díaz authored
GICv3: Allow probe for fewer GICR interfaces than exposed by the frame
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Antonio Niño Díaz authored
plat: intel: Add BL2 support for Stratix 10 SoC
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Soby Mathew authored
Previously the GICv3 redistributor probe function (gicv3_rdistif_base_addrs_probe()) asserted that the number of per-CPU redistributor interfaces expected to be probed by the platform is equal to the number exported by the redistributor frame. This is a problem in case the number of CPUs in the platform is less than the number of redistributor interfaces in the frame. Hence this patch removes the assertion check and allows probe for fewer redistributor interfaces as required by the platform. Change-Id: I3449763a3ad70817224442cbe184d001030c9874 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Antonio Niño Díaz authored
Fixes related to BL33 image on Arm platforms
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Antonio Niño Díaz authored
RPi3 SDHost driver
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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- 01 Feb, 2019 7 commits
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Id7c22d76b896d1dcac18cdb0e564ce4e02583e33 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Niño Díaz authored
Remove dead code related to LOAD_IMAGE_V2=0
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Antonio Niño Díaz authored
hikey960: EDMAC: leave channel 0 as secure
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Sandrine Bailleux authored
The BL33 image must not go past the end of DRAM. Change-Id: I56668ab760d82332d69a8904d125d9a055aa91d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Sandrine Bailleux authored
PLAT_ARM_NS_IMAGE_OFFSET is in fact not an offset relative to some base address, it is an absolute address. Rename it to avoid any confusion. Change-Id: I1f7f5e8553cb267786afe7e5f3cd4d665b610d3f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 31 Jan, 2019 5 commits
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Ying-Chun Liu (PaulLiu) authored
This patch adds myself to co-maintainer list of Raspberry Pi 3 platform. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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Ying-Chun Liu (PaulLiu) authored
This patch inits SDHost in BL2 earlysetup. BL2 can start operating mmc commands to read/write MMC raw blocks. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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Ying-Chun Liu (PaulLiu) authored
This commit adds SDHost driver for RaspberryPi3. SDHost driver uses the GPIO driver to connect the SDCard and SDHost. By using this driver it is able to read/write raw blocks on SDCard. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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Antonio Niño Díaz authored
User Guide: Move ARM_PLAT_MT doc to Arm build flags
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Varun Wadekar authored
Platforms that do not support bpmp firmware, do not need access to the PMC block from outside of the CPU complex. The agents running on the CPU can always access the PMC through the EL3 exception space. This patch restricts non-secure world access to the PMC block on such platforms. Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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