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  1. 31 Jan, 2020 2 commits
    • Varun Wadekar's avatar
      Tegra194: se: fix multiple MISRA issues · 8d4107f0
      Varun Wadekar authored 
      

This patch fixes violations for the following MISRA rules

* Rule 8.4  "A compatible declaration shall be visible when an object or
             function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
             conversions are perdormed shall have the same essential type
             category"
* Rule 17.7 "The value returned by a function having non-void return
             type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d4107f0
    • Varun Wadekar's avatar
      Tegra: remove weakly defined PSCI platform handlers · e44f86ef
      Varun Wadekar authored 
      

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e44f86ef
  3. 28 Jan, 2020 2 commits
    • Madhukar Pappireddy's avatar
      Enable -Wredundant-decls warning check · ca661a00
      Madhukar Pappireddy authored 
      

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      ca661a00
    • Varun Wadekar's avatar
      Tegra194: enable spe-console functionality · ffd58cca
      Varun Wadekar authored 
      

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ffd58cca
  5. 23 Jan, 2020 16 commits
  7. 17 Jan, 2020 10 commits
  9. 12 Jan, 2020 1 commit
  11. 09 Jan, 2020 2 commits
  13. 08 Jan, 2020 1 commit
  15. 10 Dec, 2019 2 commits
  17. 28 Nov, 2019 4 commits
    • Steven Kao's avatar
      Tegra194: memctrl: fix logic to check TZDRAM config register access · 95397d96
      Steven Kao authored 
      

This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.

Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      95397d96
    • Varun Wadekar's avatar
      Tegra: introduce plat_enable_console() · 117dbe6c
      Varun Wadekar authored 
      

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      117dbe6c
    • Steven Kao's avatar
      Tegra194: update nvg header to v6.4 · 02b3e311
      Steven Kao authored 
      

This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.

Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      02b3e311
    • Dilan Lee's avatar
      Tegra194: mce: enable strict checking · ac252f95
      Dilan Lee authored 
      

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.

This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.

Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: default avatarDilan Lee <dilee@nvidia.com>
      ac252f95