- 04 Sep, 2018 3 commits
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Siva Durga Prasad Paladugu authored
Add support for writing to AFI registers. So that after writing a bitstream the interface can be programmed. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Since the MMIO read/write APIs are removed from Linux user space, Linux cannot directly write to the Global General Storage Register 4 any more to set healthy boot status. Create an IOCTL to allow Linux to set boot health status. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Will Wong <willw@xilinx.com>
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Siva Durga Prasad Paladugu authored
To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's are controlled by BOOT_PIN_CTRL register present in CRL_APB address region. Since CRL_APB can be resticted to secure access, this pin should be controlled by ATF. This patch adds the support for the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 27 Aug, 2018 1 commit
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Rajan Vaja authored
Currently in Linux maximum number of clocks is hard-coded and so it needs to allocate static memory. It can get actual clock number after querying all clock names by special clock name string. Add new query data parameter to get actual number of clocks so Linux can get actual clock numbers in advance. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
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- 24 Jul, 2018 1 commit
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Jun, 2018 2 commits
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Siva Durga Prasad Paladugu authored
This patch reads the chipid registers directly instead of making pm call when running at BL32. User should ensure that these registers should always be accessed from APU in their system configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch builds ATF to DDR if SPD is enabled as it cant fit in On chip memory(OCM) with SPD enabled. This solves the issue of build failure with SPD enabled for ZynqMP platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 14 Jun, 2018 1 commit
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Roberto Vargas authored
RFC4122 defines that fields are stored in network order (big endian), but TF-A stores them in machine order (little endian by default in TF-A). We cannot change the future UUIDs that are already generated, but we can store all the bytes using arrays and modify fiptool to generate the UUIDs with the correct byte order. Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 17 May, 2018 27 commits
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Siva Durga Prasad Paladugu authored
This patch adds support to restart system incase of wdt timeout. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, display EG/EV as a part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field.This patch also used IPI to get this info from pmufw instead of directly accessing the registers. Accessing this info from pmufw using IPI fixes the issue of PMUFW access denied error for reading IPDISABLE register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch adds new API for processing secure images. This API is used for authentication and decryption of secure images using xilsecure in pmufw. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Tejas Patel authored
Existing code blocks each IPI send request in ipi_mb_notify() function till pmu clears respective bit in ipi observation register. After sending PM_SYSTEM_SHUTDOWN request to PMU, PMU will restart APU. While PMU is restarting APU, ATF is running out of OCM, which can cause read/write hang from/to OCM. There is no need to wait for notification from PMU in case of SystemShutdown request in ATF, as APU is going to restart. This patch fixes APU only restart issue. Signed-off-by: Tejas Patel <tejasp@xilinx.com> Acked-by: Wendy Liang <wendy.liang@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch makes bitstream load blocking call and waits until bitstream is loaded successfully or return with error. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Avesh Khan <aveshk@xilinx.com>
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Siva Durga Prasad Paladugu authored
GET_CALLBACK_DATA function is not required now. IPI mailbox can be used instead of GET_CALLBACK_DATA function. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Rajan Vaja authored
PMU IPI-1 is used for callbacks from PMU to master. Unsecure master can also receive callbacks from PMU, so make PMU IPI-1 as non-secure. All requests from master(s) to PMU would still go on PMU IPI-1 secure channel. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
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Rajan Vaja authored
Remove includes of gic_common.h and string.h which are not required. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com>
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Siva Durga Prasad Paladugu authored
Xilinx now requires the PMU FW when using ATF, so it doesn't make sense to maintain checks for the PMU FW in ATF. This also means that cases where ATF came up before the PMU FW (such as on QEMU) ATF will now hang waiting for the PMU FW instead of aborting. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
Use positive logic (pm_up instead of pm_down) to check whether PMU services are available. This change also puts the variable into the BSS section rather than the Data section as the variable is now initialized to 0 rather than 1. Signed-off-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Alistair Francis authored
If we can't find the FSBL handoff struct don't panic and just use the defaults instead. We still print a warning to the user to let them know what we couldn't find it. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
Instead of calling panic() in fsbl_atf_handover() return the error status so that bl31_early_platform_setup() can act accordingly. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Wendy Liang authored
Type "entry_point_info_t" is used in zynqmp_private.h. It is defined in "bl_common.h". The header file which defines the type should be included. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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Siva Durga Prasad Paladugu authored
Added SHA to calculate SHA3 hash,RSA to encrypt data with public key and decrypt with private key and AES to do symmetric encryption with User key or device key. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Read ipdisable reg which needs to be used for cg/eg/ev device detection. ATF runs in EL3 that's why this read can be done directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Add new id codes for RFSoC's. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch corrects the SVD mask for getting chip ID using 0xe is wrong and 0x7 is correct. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
psci system_reset and system_off calls now retrieve shutdown scope on the fly. The default scope is system, but it can be changed by calling pm_system_shutdown(2, scope) Until full support for different restart scopes becomes available with PSCI 1.1 this change allows users to set the reboot scope to match their application needs. Possible scope values: 0 - APU subsystem: does not affect RPU, PMU or PL 1 - PS only: shutdown/restart entire PS without affecting PL 2 - System: shutdown/restart applies to entire system Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
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Filip Drazic authored
The PM_INIT_FINALIZE PM API is required to inform the PFW that APU is done with requesting nodes and that not-requested nodes can be powered down. If PM is not enabled, this call will never be made and PFW will never power down any of the nodes which APU can use. Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Filip Drazic authored
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Siva Durga Prasad Paladugu authored
This patch adds pm_secure_rsaaes() API to provide access to the xilsecure library for loading secure images Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Read boot mode register using pm_mmio_read if pmu is present otherwise access it directly using mmio_read_32(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Filip Drazic authored
The pm_req_wakeup PM API accepts start address (64-bit unsiged integer) and a flag stating if address should be used. To save an argument of the SMC call, flag is encoded in the LSB of the address, since addresses are word aligned. Decode start address and use-address flag in the PM SMC handler and pass them to pm_req_wakeup. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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Filip Drazic authored
Call to pm_client_wakeup from pm_req_wakeup prevented the PM API call to be used to wake up non-APU processor (e.g. from higher ELs), since it clears power down request for specified APU processor. Move this function out of pm_client_wakeup to allow passing wake up requests to the PMU for other processor in the system. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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Mirela Simonovic authored
NODE_EXTERN is the slave node which represents an external wake source. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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Siva Durga Prasad Paladugu authored
Beside standard suspend-to-RAM state, Zynq MPSoC supports suspend-to-RAM state with additional power savings, called power-off suspend-to-RAM. If this mode is set, only NODE_EXTERN must be set as wake source. Standard suspend-to-RAM procedure is unchanged. This patch adds support for setting suspend mode from higher ELs and ensuring that all conditions for power-off suspend mode are set. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Anes Hadziahmetagic authored
pm_get_node_status API function returns 3 values: -status: Current power state of the node -requirements: Current requirements for the node -usage: Current usage of the node The last two values only apply to slave nodes. Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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- 27 Apr, 2018 2 commits
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Masahiro Yamada authored
Since commit 031dbb12 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Commit 4c0d0390 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 26 Mar, 2018 1 commit
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Jonathan Wright authored
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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- 15 Mar, 2018 1 commit
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Jolly Shah authored
Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
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