- 27 Oct, 2016 1 commit
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davidcunado-arm authored
fiptool: Link `toc_entry` and `image` structures via UUID
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- 26 Oct, 2016 2 commits
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davidcunado-arm authored
rockchip: optimize the link mechanism for SRAM code
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davidcunado-arm authored
rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5
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- 24 Oct, 2016 5 commits
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Caesar Wang authored
The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to the test result on rk3399, the A72 will need lower voltage for high frequency if it's set to be 5, and almost no effect on performance. Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Caesar Wang authored
Due to the PMU design, the PMU may not clear the WAKEUP bit after wakeup, therefore, the state machine at the power mode may enter the infinite loop during WFI. There is a solution that we can use the M0 to monitor the WAKEUP bit and clear it during power mode, then the state machine will be recovered immediately. Then, the DUT can exit the WFI normally. Change-Id: I303628553b728c214bf2d436bd3122032b5e669c Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Caesar Wang authored
This CL supports add M0 source code to built into the bl31.bin, the goal is that we can load the M0 code binary into SRAM and execute it. We need the M0 help us to clean the power_mode_en bit during the AP PMU enter the state machine with interrupt, and avoid to the AP can not exit the loop forever. Change-Id: I844582c54a1f0d44ca41290d44618df58679f341 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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Caesar Wang authored
Add the common extra.ld.S and customized rk3399.ld.S to extend to more features for different platforms. For example, we can add SRAM section and specific address to load there if we need it, and the common bl31.ld.S not need to be modified. Therefore, we can remove the unused codes which copying explicitly from the function pmusram_prepare(). It looks like more clear. Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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davidcunado-arm authored
rockchip: fixes the wrong CLKSEL_CON count for CRU
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- 21 Oct, 2016 1 commit
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Caesar Wang authored
The CRU_CLKSEL_COUNT value is 108, not 0x108. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Change-Id: Ib9db066b8b3ecafcee7f645dd5633b55a808e3d7
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- 18 Oct, 2016 2 commits
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danh-arm authored
partition: check GPT partition table
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dp-arm authored
The `toc_entry` and `image` data structures had a cyclic relationship. This patch removes the explicit dependencies and introduces functions to link them via the UUID. This change highlights the intent of the code better and makes it more flexible for future enhancements. Change-Id: I0c3dd7bfda2a631a3827c8ba4831849c500affe9 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 17 Oct, 2016 4 commits
- 14 Oct, 2016 2 commits
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davidcunado-arm authored
rockchip: fixes the clock select and divide register for rk3399
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Soby Mathew authored
The values of CP15BEN, nTWI & nTWE bits in SCTLR_EL1 are architecturally unknown if EL3 is AARCH64 whereas they reset to 1 if EL3 is AArch32. This might be a compatibility break for legacy AArch32 normal world software if these bits are not set to 1 when EL3 is AArch64. This patch enables the CP15BEN, nTWI and nTWE bits in the SCTLR_EL1 if the lower non-secure EL is AArch32. This unifies the SCTLR settings for lower non-secure EL in AArch32 mode for both AArch64 and AArch32 builds of Trusted Firmware. Fixes ARM-software/tf-issues#428 Change-Id: I3152d1580e4869c0ea745c5bd9da765f9c254947 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 13 Oct, 2016 6 commits
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davidcunado-arm authored
Final updates for v1.3 release
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davidcunado-arm authored
Release v1.3: Minor updates to user guide
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David Cunado authored
Updated the user guide to clarify building FIP for AArch32. The instructions were previously specific to building a FIP for AArch64. Change-Id: I7bd1a6b8e810cfda411f707e04f479006817858e Signed-off-by: David Cunado <david.cunado@arm.com>
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Dan Handley authored
Update the release notes (readme.md) for the ARM Trusted Firmware v1.3 release. Change-Id: Ia1f4eb1897e63eeab7d69a593ba0ad91d50043f5 Signed-off-by: Dan Handley <dan.handley@arm.com>
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David Cunado authored
Change-Id: I05991543d28e70b67be600b714990af6a8d7ba29
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David Cunado authored
Updated change-log.md with summary of changes since release v1.2. Change-Id: Ia1e18ff4b0da567cf12dfcb53e6317e995100bdf
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- 12 Oct, 2016 11 commits
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danh-arm authored
PMF: Add documentation
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dp-arm authored
Add a Performance Measurement Framework (PMF) section to the firmware design document. Change-Id: I5953bd3b1067501f190164c8827d2b0d8022fc0b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
This include provides nothing useful for TF and prevents building the fiptool using musl libc[0]. [0] https://www.musl-libc.org/ Change-Id: Ied35e16b9ea2b40213433f2a8185dddc59077884 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
In order to quantify the overall time spent in the PSCI software implementation, an initial collection of PMF instrumentation points has been added. Instrumentation has been added to the following code paths: - Entry to PSCI SMC handler. The timestamp is captured as early as possible during the runtime exception and stored in memory before entering the PSCI SMC handler. - Exit from PSCI SMC handler. The timestamp is captured after normal return from the PSCI SMC handler or if a low power state was requested it is captured in the bl31 warm boot path before return to normal world. - Entry to low power state. The timestamp is captured before entry to a low power state which implies either standby or power down. As these power states are mutually exclusive, only one timestamp is defined to describe both. It is possible to differentiate between the two power states using the PSCI STAT interface. - Exit from low power state. The timestamp is captured after a standby or power up operation has completed. To calculate the number of cycles spent running code in Trusted Firmware one can perform the following calculation: (exit_psci - enter_psci) - (exit_low_pwr - enter_low_pwr). The resulting number of cycles can be converted to time given the frequency of the counter. Change-Id: Ie3b8f3d16409b6703747093b3a2d5c7429ad0166 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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dp-arm authored
This patch adds ARM SiP service for use by ARM standard platforms. This service is added to support the SMC interface for the Performance measurement framework(PMF). Change-Id: I26f5712f9ab54f5f721dd4781e35a16f40aacc44 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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danh-arm authored
Fix documentation of bootwrapper boot on juno
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Antonio Nino Diaz authored
The user guide incorrectly claimed that it is possible to load a bootwrapped kernel over JTAG on Juno in the same manner as an EL3 payload. In the EL3 payload boot flow, some of the platform initialisations in BL2 are modified. In particular, the TZC settings are modified to allow unrestricted access to DRAM. This in turn allows the debugger to access the DRAM and therefore to load the image there. In the BL33-preloaded boot flow though, BL2 uses the default TZC programming, which prevent access to most of the DRAM from secure state. When execution reaches the SPIN_ON_BL1_EXIT loop, the MMU is disabled and thus DS-5 presumably issues secure access transactions while trying to load the image, which fails. One way around it is to stop execution at the end of BL2 instead. At this point, the MMU is still enabled and the DRAM is mapped as non-secure memory. Therefore, the debugger is allowed to access this memory in this context and to sucessfully load the bootwrapped kernel in DRAM. The user guide is updated to suggest this alternative method. Co-Authored-By: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Dan Handley <dan.handley@arm.com> Change-Id: I537ea1c6d2f96edc06bc3f512e770c748bcabe94
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danh-arm authored
AArch32: Update firmware-design.md
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danh-arm authored
AArch32: Update user-guide and add DTBs
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danh-arm authored
Fix GICv3 DT to include psci system off/reset
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danh-arm authored
Docs: Rename duplicate title in porting guide
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- 11 Oct, 2016 4 commits
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Soby Mathew authored
This patch adds necessary updates for building and running Trusted Firmware for AArch32 to user-guide.md. The instructions for running on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and `FVP_Base_Cortex-A32x4` models are added. The device tree files for AArch32 Linux kernel are also added in the `fdts` folder. Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e
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Yatharth Kochar authored
This patch updates the firmware-design.md for AArch32 related changes. Change-Id: Idf392a44861ab9c1f59f3de4f3435f508b17c678
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Jeenu Viswambharan authored
Fix one of the two titles that ended up being the same, although both describe different things. Change-Id: I66ecf369643709898ee4c014659d8f85c0480643
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Soby Mathew authored
The `fvp-base-gicv3-psci` and `fvp-foundation-gicv3-psci` device tree source files did not have psci node entries for `system off` and `system reset`. Also the DTS files included `rtsm_ve-motherboard-no_psci.dtsi` instead of `rtsm_ve-motherboard.dtsi`. As a result, the Linux kernel failed to invoke the PSCI_SYSTEM_OFF/RESET API when being shutdown/reset. This patch corrects this problem and also updates the corresponding DTB files. This patch also removes `rtsm_ve-motherboard-no_psci.dtsi` and `fvp-foundation-motherboard-no_psci.dtsi` files as they are no longer used. Change-Id: I8ba61a1323035f7508cae663bb490ac0e8a64618
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- 10 Oct, 2016 1 commit
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Andreas Färber authored
Insert a cosmetic space before "(FIP)". Signed-off-by: Andreas Färber <afaerber@suse.de>
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- 29 Sep, 2016 1 commit
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davidcunado-arm authored
AArch32: Add `memcpy4` function in assembly
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