Signed-off-by: Jon Medhurst <tixy@linaro.org>

BL30 needs an entry in the table in io_fip.c.  I made it #ifdef'd so
that ports that don't use a BL30 won't break.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Removing semihosting from the plat_io_storage code copied from FVP.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Juno has a "taped out" BL1.

To run your own BL1 on the board, you have to place it in a "ROM bypass"
address and configure the platform to boot from there.

The agreed bypass address is an offset of 0x03EC0000 from the start of
NOR flash (0x08000000), which equates to 0x0BEC0000.

To run the model using a BL1 in bypass mode, you should use a parameter
set something like this:

	<path to>/FVP_CSS_Juno3 \
		-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
		--data css.cluster1.cpu0=bl1.bin@0x0BEC0000 \
		-C soc.scc.apps_alt_boot=0x0BEC0000

To build BL1 as a ROM located at address zero, you can over-ride the
default value for TZROM_BASE by passing parameters to make, eg:

	ASFLAGS="-D TZROM_BASE=0x00000000" \
	CFLAGS="-D TZROM_BASE=0x00000000" \
	CROSS_COMPILE=aarch64-linux-gnu- \
	make PLAT=juno DEBUG=1 all

Then you can launch the model using a command such as:

	<path to>/FVP_CSS_Juno3 \
		-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
		-C css.trustedBootROMloader.fname=<path to>/bl1.bin \
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Currently UEFI and Linux are using SMC calls in the 'ARM Architecture'
Owning Entity range so lets implement these to get things working.

UEFI probably doesn't actually need to issue the ID_PRESENCE and ID_UID
calls it does, and the device-tree used by Linux could specify the PSCI
identifiers instead. After those changes, this patch isn't required.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

This is a temporary solution for issue #20
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

The SCP Ready command is sent by the SCP to indicate that the BL3-0 RAM
Firmware image is successfully up and running.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Note, on Juno mailboxes are 16 bytes because any bigger and they would
overlap the memory used for MHU payload data for SCP->AP transfers.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Juno doesn't have TZDRAM as FVP does, and there is real reason why we
need a special memory region for bl31_args anyway, assuming we take care
to copy it in BL31 before BL2's memory is reused.
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Signed-off-by: Jon Medhurst <tixy@linaro.org>

At present, bl1_arch_setup() and bl31_arch_setup() program the counter
frequency using a value from the memory mapped generic timer. The
generic timer however is not necessarily present on all ARM systems
(although it is architected to be present on all server systems).

This patch moves the timer setup to platform-specific code and updates
the relevant documentation. Also, CNTR.FCREQ is set as the specification
requires the bit corresponding to the counter's frequency to be set when
enabling. Since we intend to use the base frequency, set bit 8.

Fixes ARM-software/tf-issues#24

Change-Id: I32c52cf882253e01f49056f47c58c23e6f422652

This patch removes the 'CPU present' flag that's being set but not
referred or used anywhere else.

Change-Id: Iaf82bdb354134e0b33af16c7ba88eb2259b2682a

Remove the instructions to update the change log from
contribution.md. The change log no longer contains a
"Detailed changes since last release" section.

Also, update the documentation links following recent
documentation changes.

Change-Id: Id9df43d666f7f9a60dcc6f663a8a85cdd2ff7cc4

Fixes ARM-software/tf-issues#42

Some callers of load_image() may need to get the size of the image
before/after loading it.

Change-Id: I8dc067b69fc711433651a560ba5a8c3519445857
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Fixes ARM-software/tf-issues#41

The policy functions for each file to be loaded were implemented by
copy/pasting one method and then varying the data checked.

This patch creates a generic function to check the policy based on the
data stored in a table.

This removes the amount of duplicated code but also makes the code
simpler and more efficient.

Change-Id: I1c52eacf6f18a1442dabbb33edd03d4bb8bbeae0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

If a platform doesn't specify a BLx_SOURCE variable, then building
of the corresponding bootloader isn't attempted. Also allow BL3-3 to
be omitted from the FIP.

Note, this change also removes support for PLAT=all and the 'fip' target
from the 'all' recipe.

Fixes ARM-software/tf-issues#30

Change-Id: Ibdfead0440256eaf364617ecff65290ca6fe6240
Signed-off-by: Jon Medhurst <tixy@linaro.org>

So it updates each time a bootloader changes, not just when bl*_main.c
files are recompiled.

Fixes ARM-software/tf-issues#33

Change-Id: Ie8e1a7bd7e1913d2e96ac268606284f76af8c5ab
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Change-Id: I559c5a4d86cad55ce3f6ad71285b538d3cfd76dc
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Change-Id: I5b8d040ebc6672e40e4f13925e2fd5bc124103f4
Signed-off-by: Jon Medhurst <tixy@linaro.org>

This change requires all platforms to now specify a list of source files
rather than object files.

New source files should preferably be specified by using the path as
well and we should add this in the future for all files so we can remove
use of vpath. This is desirable because vpath hides issues like the fact
that BL2 currently pulls in a BL1 file bl1/aarch64/early_exceptions.S
and if in the future we added bl2/aarch64/early_exceptions.S then it's
likely only one of the two version would be used for both bootloaders.

This change also removes the 'dump' build target and simply gets
bootloaders to always generate a dump file. At the same time the -x
option is added so the section headers and symbols table are listed.

Fixes ARM-software/tf-issues#11

Change-Id: Ie38f7be76fed95756c8576cf3f3ea3b7015a18dc
Signed-off-by: Jon Medhurst <tixy@linaro.org>

Make gicd_set_ipriorityr() actually write to the priority register.

Also correct callers of this function which want the highest priority
to use the value zero as this is the highest priority value according
to the ARM Generic Interrupt Controller Architecture Specification.

To make this easier to get right, we introduce defines for the lowest
and highest priorities for secure and non-secure interrupts.

Fixes ARM-software/tf-issues#21
Signed-off-by: Jon Medhurst <tixy@linaro.org>

bakery_lock_release() expects an mpidr as the first argument however
bakery_lock_release() is calling it with the 'entry' argument it has
calculated. Rather than fixing this to pass the mpidr value it would be
much more efficient to just replace the call with

   assert(bakery->owner == entry)

As this leaves no remaining users of bakery_lock_held(), we might as
well delete it.

Fixes ARM-software/tf-issues#27
Signed-off-by: Jon Medhurst <tixy@linaro.org>