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Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.
Signed-off-by: Will Wong <willw@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702

Merge "plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB" into integration

* changes:
  plat/arm: rename rddanielxlr to rdv1mc
  plat/arm: rename rddaniel to rdv1

ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ia095d118121e6f75e8d320e87d5e2018068fa079

The current configuration of CPU windows on Armada 37x0 with 4 GB DRAM
can only utilize 3.375 GB of memory. This is because there are only 5
configuration windows, configured as such (in hexadecimal, also showing
ranges not configurable by CPU windows):

         0 - 80000000 |   2 GB | DDR  | CPU window 0
  80000000 - C0000000 |   1 GB | DDR  | CPU window 1
  C0000000 - D0000000 | 256 MB | DDR  | CPU window 2
  D0000000 - D2000000 |  32 MB |      | Internal regs
      empty space     |        |      |
  D8000000 - D8010000 |  64 KB |      | CCI regs
      empty space     |        |      |
  E0000000 - E8000000 | 128 MB | DDR  | CPU window 3
  E8000000 - F0000000 | 128 MB | PCIe | CPU window 4
      empty space     |        |      |
  FFF00000 - end      |  64 KB |      | Boot ROM

This can be improved by taking into account that:
- CCI window can be moved (the base address is only hardcoded in TF-A;
  U-Boot and Linux will not break with changing of this address)
- PCIe window can be moved (upstream U-Boot can change device-tree
  ranges of PCIe if PCIe window is moved)

Change the layout after the Internal regs as such:

  D2000000 - F2000000 | 512 MB | DDR  | CPU window 3
  F2000000 - FA000000 | 128 MB | PCIe | CPU window 4
      empty space     |        |      |
  FE000000 - FE010000 |  64 KB |      | CCI regs
      empty space     |        |      |
  FFF00000 - end      |  64 KB |      | Boot ROM

(Note that CCI regs base address is moved from D8000000 to FE000000 in
 all cases, not only for the configuration with 4 GB of DRAM. This is
 because TF-A is built with this address as a constant, so we cannot
 change this address at runtime only on some boards.)

This yields 3.75 GB of usable RAM.

Moreover U-Boot can theoretically reconfigure the PCIe window to DDR if
it discovers that no PCIe card is connected. This can add another 128 MB
of DRAM (resulting only in 128 MB of DRAM not being used).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4ca1999f852f90055fac8b2c4f7e80275a13ad7e

* changes:
  drivers: renesas: rcar: io: Code cleanup
  drivers: renesas: rcar: pwrc: Code cleanup
  drivers: renesas: rcar: common: Code cleanup
  drivers: renesas: rcar: watchdog: Fix typo
  drivers: renesas: rcar: scif: Fix coding style
  drivers: renesas: rcar: iic_dvfs: Fix coding style

* changes:
  drivers: renesas: rcar: dma: Fix coding style
  drivers: renesas: rcar: delay: Fix checkpatch warnings
  drivers: renesas: rcar: avs: Fix checkpatch warnings
  drivers: renesas: rcar: auth: Use space instead of TAB

Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.

Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f

This patch fixes checkpatch warnings and arrange header
as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I46cd4d9b2851202324fe714e776cf3ad2ee1d923

Sort the headers alphabetically and replace TAB with a space
after #define.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I07c358294b7c02cbfa360112bbbde0eb5f2b50f5

This patches fixes checkpatch warnings, replace TAB with space
after #define macros and arrange header as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iba009587e0b499b3ae58876be390602ae14175b2

Fix checkpatch warnings.

There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iec7dd019bd38e84eccd8cc17189745fdef1911bb

This patch fixes the below checkpatch warnings
 Line 13: WARNING: please, no spaces at the start of a line
 Line 15: WARNING: please, no spaces at the start of a line
 Line 18: WARNING: Missing a blank line after declarations
 Line 24: WARNING: please, no spaces at the start of a line
 Line 26: WARNING: please, no spaces at the start of a line
 Line 29: WARNING: Missing a blank line after declarations
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I41d146e86889640d11e88c0717039353ddceff0d

Fix checkpatch warnings.

There are no functional changes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic7406aa88e121914270a8d192f170c9c4244578a

Fix the typo "occured" -> "occurred"
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Ic66ceab364f7dc926dc6a6db641ca173601cd031

Use space instead of TAB after #define's. Also updated
header files as per TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I4eac94f0bc79f24b8ac7165ec48f1e1de95d7205

Replace TAB with space after #define macros and update comments as per
TF-A coding style.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: Iff46838a41f991f7dd9dc6fb043e9e482ea0b11d

Sort the header includes alphabetically, fix typos and drop unneeded TAB
and replace it with space
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I62e2658b0309c0985dd32ff023b8b16bd7f2be8e

Reference Design platform RD-Daniel-ConfigXLR has been renamed to
RD-V1-MC. Correspondingly, remove all uses of 'rddanielxlr' and replace
it with 'rdv1mc' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I5d91c69738397b19ced43949b4080c74678e604c

Reference Design platform RD-Daniel has been renamed to RD-V1.
Correspondingly, remove all uses of 'rddaniel' and replace it with
'rdv1' where appropriate.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I1702bab39c501f8c0a09df131cb2394d54c83bcf

This patch fixes the non compliant code like missing braces for
conditional single statement bodies.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I95b410ae5950f85dc913c4448fcd0a97e0fd490c

Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration

* changes:
  plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
  plat: zynqmp: Check for DLL status before doing reset

This patch provides the following changes in fixup_gdt_reloc()
function:
- Fixes assertions in processing dynamic relocations, when
relocation entries not matching R_AARCH64_RELATIVE type are found.
Linker might generate entries of relocation type R_AARCH64_NONE
(code 0), which should be ignored to make the code boot. Similar
issue was fixed in OP-TEE (see optee_os/ldelf/ta_elf_rel.c
commit 7a4dc765c133125428136a496a7644c6fec9b3c2)
- Fixes bug when "b.ge" (signed greater than or equal) condition
codes were used instead of "b.hs" (greater than or equal) for
comparison of absolute addresses.
- Adds optimisation which skips fixing Global Object Table (GOT)
entries when offset value is 0.

Change-Id: I35e34e055b7476843903859be947b883a1feb1b5
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Introduce a new build option CM3_SYSTEM_RESET for A3700 platform, which,
when enabled, adds code to the PSCI reset handler to try to do system
reset by the WTMI firmware running on the Cortex-M3 secure coprocessor.
(This function is exposed via the mailbox interface.)

The reason is that the Turris MOX board has a HW bug which causes reset
to hang unpredictably. This issue can be solved by putting the board in
a specific state before reset.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3f60b9f244f334adcd33d6db6a361fbc8b8d209f

* changes:
  xilinx: zynqmp: Add support for Error Management
  zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
  zynqmp : pm : Adds new zynqmp-pm api SMC call for register access

Adding the EM specific smc handler for the EM-related requests.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98122d49604a01a2f6bd1e509a5896ee68069dd0

This patch adds new api to access zynqmp efuse memory
Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I0971ab6549552a6f96412431388d19b822db00ab

This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.
Signed-off-by: Kalyani Akula <kalyania@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042

This patch fixes AXG platform build error:
plat/amlogic/axg/axg_pm.c: In function 'axg_pwr_domain_off':
plat/amlogic/axg/axg_pm.c:124:43: error: array subscript 2
 is above array bounds of 'const plat_local_state_t[2]'
 {aka 'const unsigned char[2]'}
by changing PLAT_MAX_PWR_LVL from MPIDR_AFFLVL1 to MPIDR_AFFLVL2
in plat\amlogic\axg\include\platform_def.h.

Change-Id: I9a701e8f26231e62f844920aec5830664f3fb324
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

* changes:
  ti: k3: Introduce lite device board support
  ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
  ti: k3: Move USE_COHERENT_MEM only for the generic board
  ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
  ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
  ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
  ti: k3: common: Enable A72 erratum 1319367
  ti: k3: common: Enable A53 erratum 1530924
  maintainers: Update maintainers for TI port

Implementation is simple, just wait for the TX FIFO to be empty.

Without this patch TF-A on A3720 truncate the last line:

  NOTICE:  BL31: Built : 16:1

With this patch TF-A on A3720 print correctly also the last line:

  NOTICE:  BL31: Built : 19:03:31, Dec 23 2020
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09