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  1. 23 Jan, 2019 3 commits
  3. 18 Jan, 2019 6 commits
    • Harvey Hsieh's avatar
      Tegra: memctrl: clean MC INT status before exit to bootloader · 650d9c52
      Harvey Hsieh authored 
      

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.

Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: default avatarHarvey Hsieh <hhsieh@nvidia.com>
      650d9c52
    • Harvey Hsieh's avatar
      Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO · 70da35b0
      Harvey Hsieh authored 
      

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: default avatarHarvey Hsieh <hhsieh@nvidia.com>
      70da35b0
    • Varun Wadekar's avatar
      Tegra: memctrl: assert if dynamic memmap fails · 7a6e0537
      Varun Wadekar authored 
      

This patch adds an assert in case the dynamic memmap routine fails.

Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      7a6e0537
    • Anthony Zhou's avatar
      Tegra: fix defects flagged by MISRA Rule 10.3 · aa64c5fb
      Anthony Zhou authored 
      

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      aa64c5fb
    • Anthony Zhou's avatar
      Tegra: common: fix defects flagged by MISRA scan · 4c994002
      Anthony Zhou authored 
      

Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.

Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]

Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      4c994002
    • Anthony Zhou's avatar
      Tegra: common: drivers: fix MISRA defects · 61beb3e0
      Anthony Zhou authored 
      

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operation [Rule 12.4]

Voided non c-library functions whose return types are not used
 [Rule 17.7]

Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      61beb3e0
  5. 16 Jan, 2019 1 commit
    • Krishna Reddy's avatar
      Tegra186: memctrl_v2: Set MC clients ordering as per client needs · b86e691e
      Krishna Reddy authored 
      

Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.

SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.

Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2
Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
      b86e691e
  7. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  9. 15 Jun, 2017 2 commits
  11. 03 May, 2017 1 commit
  13. 01 May, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: zero out NS Video memory carveout region · 9d42d23a
      Varun Wadekar authored 
      

The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.

This patch adds the logic to zero out the previous memory carveout
region.

Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      9d42d23a
  15. 13 Apr, 2017 3 commits
  17. 07 Apr, 2017 4 commits
  19. 05 Apr, 2017 3 commits
  21. 30 Mar, 2017 2 commits
  23. 27 Mar, 2017 1 commit
  25. 23 Mar, 2017 5 commits
  27. 22 Mar, 2017 1 commit
  29. 20 Mar, 2017 6 commits