- 16 Jan, 2019 21 commits
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Varun Wadekar authored
This patch fixes the logic to check if Atomics hardware block is powered on during boot Reported by: Peter De Schrijver <pdeschrijver@nvidia.com> Change-Id: I4a6521bcee37225d1402321151c48fa631776b8a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch updates the macros to include the newly added IRAM memory apertures. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch removes unwanted error prints from the MCE command handler, to reduce the code complexity for this function. Tested with 'pmccabe' Change-Id: I375d289db1df9e119eeb1830210974457c8905a4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes support for the SC8 power state as the feature is no longer required for Tegra186 projects. Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
* EKS blob size was not passed by as a boot parameter earlier. Its being passed now * If EKS value sent by bootloader is non-zero update the boot parameter from default value to the argument passed by bootloader Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098 Signed-off-by: Akshay Sharan <asharan@nvidia.com>
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Sam Payne authored
DRBG must be initialized to guarantee SRK has a random value during suspend. This patch add a sequence to generate an SRK on boot and during resume for SE1 and SE2. This SRK value is not saved to PMC scratch, and should be overwitten during atomic suspend. Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c Signed-off-by: Sam Payne <spayne@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch fixes MISRA defects for the MCE driver. * Using logical NOT for bool type function * Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace MPIDR_CLUSTER_MASK Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
This patch uses int32_t to replace ints, to fix Rule 4.6 of the MISRA standard. Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds (void) for unused function parameters to fix Rule 2.7 of the MISRA standard. Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch sets up the clock for the UART console, for real Silicon and FPGA platforms. FPGA platforms run the UART clock source at 13MHz, whereas the clock cource runs at 408MHz for real silicon. Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds helper functions to find out the chip ID of the Tegra SoC. Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The platform code generates the power domain tree. The handler to retrieve the tree should also reside in the platform code. This patch moves the plat_get_power_domain_tree_desc() to the individual platforms. Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds support for simulation platforms as well as fixes issues flagged by the MISRA scans. Main MISRA fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix return type doesn't match the function type [Rule 10.3] * Use single return point instead of multiple [Rule 15.5] * Change return type for the tegra_platform_is_x handlers to bool Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 2 commits
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Varun Wadekar authored
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds a macro to allow platforms to compile native GICv2 drivers along with Tegra handlers. Change-Id: I8281796c09dae5704cff2daab831395d65e261b7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 25 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Even though at this point plat_crash_console_flush is optional, it will stop being optional in a following patch. The console driver of warp7 doesn't support flush, so the implementation is a placeholder. TI had ``plat_crash_console_init`` and ``plat_crash_console_putc``, but they weren't global so they weren't actually used. Also, they were calling the wrong functions. imx8_helpers.S only has placeholders for all of the functions. Change-Id: I8d17bbf37c7dad74e134c61ceb92acb9af497718 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 13 Jul, 2018 1 commit
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Sandrine Bailleux authored
With commit cf24229e ("Run compiler on debug macros for type checking"), the compiler will now always evaluate INFO() macro calls, no matter the LOG_LEVEL value. Therefore, any variable referenced in the macro has to be be defined. Address this issue by removing the local variable and using the expression it was assigned directly in the INFO() call. Change-Id: Iedc23b3538c1e162372e85390881e50718e50bf3 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 27 Apr, 2018 2 commits
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Masahiro Yamada authored
Since commit 031dbb12 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Commit 4c0d0390 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 27 Mar, 2018 1 commit
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Joel Hutton authored
Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type. Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 08 Mar, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Feb, 2018 1 commit
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Arve Hjønnevåg authored
Fixes tegra build with SPD=trusty. Not tested. Change-Id: I851a2b00b8b1cc65112b6088980a811d8eda1a99
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- 17 Feb, 2018 1 commit
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Andreas Färber authored
Commit fdb1964c ("xlat: Introduce MAP_REGION2() macro") added a granularity field to mmap_region_t. Tegra platforms were using the v2 xlat_tables implementation in common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c where arrays are being defined. This caused the next physical address to be read as granularity, causing EINVAL error and triggering an assert. Consistently use xlat_tables_v2.h header to avoid this. Fixes ARM-software/tf-issues#548. Signed-off-by: Andreas Färber <afaerber@suse.de>
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- 30 Nov, 2017 1 commit
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David Cunado authored
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero. This has a minor performance improvement with no functional impact. Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 21 Sep, 2017 1 commit
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Antonio Nino Diaz authored
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in AArch64. This is inconsistent and that's why we avoid using it as per the Coding Guidelines. This patch changes all `UL` occurrences to `U` or `ULL` depending on the context so that the size of the constant is clear. This problem affected the macro `BIT(nr)`. As long as this macro is used to fill fields of registers, that's not a problem, since all registers are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the macro is used to fill the fields of a 64-bit integer, it won't be able to set the upper 32 bits in AArch32. By changing the type of this macro to `unsigned long long` the behaviour is always the same regardless of the architecture, as this type is 64-bit wide in both cases. Some Tegra platform files have been modified by this patch. Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 29 Aug, 2017 1 commit
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Eleanor Bonnici authored
CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since ACTLR_EL1 is a different register (not implemented in Cortex-A57) this patch renames this macro for clarity. Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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- 15 Aug, 2017 1 commit
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Julius Werner authored
Assembler programmers are used to being able to define functions with a specific aligment with a pattern like this: .align X myfunction: However, this pattern is subtly broken when instead of a direct label like 'myfunction:', you use the 'func myfunction' macro that's standard in Trusted Firmware. Since the func macro declares a new section for the function, the .align directive written above it actually applies to the *previous* section in the assembly file, and the function it was supposed to apply to is linked with default alignment. An extreme case can be seen in Rockchip's plat_helpers.S which contains this code: [...] endfunc plat_crash_console_putc .align 16 func platform_cpu_warmboot [...] This assembles into the following plat_helpers.o: Sections: Idx Name Size [...] Algn 9 .text.plat_crash_console_putc 00010000 [...] 2**16 10 .text.platform_cpu_warmboot 00000080 [...] 2**3 As can be seen, the *previous* function actually got the alignment constraint, and it is also 64KB big even though it contains only two instructions, because the .align directive at the end of its section forces the assembler to insert a giant sled of NOPs. The function we actually wanted to align has the default constraint. This code only works at all because the linker just happens to put the two functions right behind each other when linking the final image, and since the end of plat_crash_console_putc is aligned the start of platform_cpu_warmboot will also be. But it still wastes almost 64KB of image space unnecessarily, and it will break under certain circumstances (e.g. if the plat_crash_console_putc function becomes unused and its section gets garbage-collected out). There's no real way to fix this with the existing func macro. Code like func myfunc .align X happens to do the right thing, but is still not really correct code (because the function label is inserted before the .align directive, so the assembler is technically allowed to insert padding at the beginning of the function which would then get executed as instructions if the function was called). Therefore, this patch adds a new parameter with a default value to the func macro that allows overriding its alignment. Also fix up all existing instances of this dangerous antipattern. Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 31 Jul, 2017 1 commit
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Varun Wadekar authored
This patch implements the early suspend handler for Tegra SoCs. This handler is empty for now and the actual support for a particular platform would be added later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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