- 04 Dec, 2020 1 commit
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Venkatesh Yadav Abbarapu authored
Update the xilinx platform makefile to include GICv2 makefile instead of adding the individual files. Updating this change as per the latest changes done in the commit #1322dc94 . Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8
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- 01 Dec, 2020 2 commits
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Masato Fukumori authored
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB. sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If qemu is configured with 512 cpus, region size used by qemu is greater than 4KB. Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org> Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
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Christoph Müllner authored
It uses the system timer as "entropy" source in the same way as QEMU, layerscape and others. Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac Signed-off-by: Christoph Müllner <christophm30@gmail.com>
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- 30 Nov, 2020 1 commit
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Javier Almansa Sobrino authored
Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
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- 20 Nov, 2020 1 commit
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Tanmay Jagdale authored
Include libraries needed to emulate Cortex-A72 on sbsa-ref target of QEMU. Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org> Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba
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- 19 Nov, 2020 5 commits
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Manish V Badarkhe authored
Renamed SMC API from "plat_smccc_feature_available" to "plat_is_smccc_feature_available" as per the current implementation. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ib0fa400816fba61039c2029a9e127501a6a36811
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Saurabh Gorecha authored
renamed smcc api with correct name plat_is_smccc_feature_available Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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Pali Rohár authored
Marvell's TF-A fork has SUBVERSION set to devel-18.12.2. The only differences between Marvell's devel-18.12.0 and devel-18.12.2 versions are documentation updates and cherry-picked patches from TF-A upstream repository. So upstream TF-A has already all changes from Marvell's TF-A devel-18.12.2 fork and therefore update SUBVERSION to reflect this state. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ce946a5176a5cbf124acd8037392463d586b072
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Pali Rohár authored
This new target builds boot-image.bin binary as described in documentation. This image does not contain WTMI image and therefore WTP repository is not required for building. Having ability to build just this boot-image.bin binary without full flash-image.bin is useful for A3720 Turris MOX board which does not use Marvell's WTP and a3700_utils. To reduce duplicity between a8k and a3k code, define this new target and also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file marvell_common.mk. For this purpose it is needed to include plat/marvell/marvell.mk file from a3700_common.mk unconditionally (and not only when WTP is defined). Now when common file plat/marvell/marvell.mk does not contain definition for building $(DOIMAGETOOL), it is possible to move its inclusion at the top of the a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
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Pali Rohár authored
Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL) variable points to external pre-compiled Marvell x86_64 ELF linux binary from A3700-utils-marvell WTP repository. It means that currently it is not possible to compile TF-A for A3720 on other host platform then linux x86_64. Part of the A3700-utils-marvell WTP repository is also source code of $(DOIMAGETOOL) TBB_Linux tool. This change adds support for building $(DOIMAGETOOL) also for a3k platform. After running $(MAKE) at appropriate subdirectory of A3700-utils-marvell WTP repository, compiled TBB_linux tool will appear in WTP subdirectory wtptp/src/TBB_Linux/release/. So update also $(DOIMAGETOOL) variable to point to the correct location where TBB_linux was built. To build TBB_linux it is required to compile external Crypto++ library which is available at: https://github.com/weidai11/cryptopp.git User needs to set CRYPTOPP_PATH option to specify path to that library. After this change it is now possible to build whole firmware for A3720 platform without requirement to use pre-compiled/proprietary x86_64 executable binaries from Marvell. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I6f26bd4356778a2f8f730a223067a2e550e6c8e0
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- 12 Nov, 2020 4 commits
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David Horstmann authored
Fix a number of typos and misspellings in TF-A documentation and comments. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee
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Venkatesh Yadav Abbarapu authored
From GCC-9 implementation of switch case was generated through jump tables, because of which we are seeing 1MB increase in rodata section. To reduce the size we are recommending to use fno-jump-tables. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I069733610809b8299fbf641f0ae35b359a8afd69
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Davorin Mista authored
All EEMI error codes start with value 2000. Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by current ATF code have been left in place. Signed-off-by: Davorin Mista <davorin.mista@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6
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Mirela Simonovic authored
Linux clock framework cannot properly deal with these errors. When the error is related to the lack of permissions to control the clock we filter the error and report the success to linux. Before recent changes in clock framework across the stack, this was done in the PMU-FW as a workaround. Since the PMU-FW now handles clocks and the permissions to control them using general principles rather than workarounds, it can no longer distinguish such exceptions and it has to return no-access error. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I1491a80e472f44e322a542b29a20eb1cb3319802
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- 28 Oct, 2020 4 commits
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David Horstmann authored
Currently, when RECLAIM_INIT_CODE is set, the stacks are scaled to ensure that the entirety of the init section can be reclaimed as stack. This causes an issue in lib/psci/aarch64/psci_helpers.S, where the stack size is used for cache operations in psci_do_pwrdown_cache_maintenance(). If the stacks are scaled, then the PSCI code may fail to invalidate some of the stack memory before power down. Resizing stacks is also not good for stability in general, since code that works with a small number of cores may overflow the stack when the number of cores is increased. Change to make every stack be PLATFORM_STACK_SIZE big, and allow the total stack to be smaller than the init section. Any pages of the init section not reclaimed as stack will be set to read-only and execute-never, for security. Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8 Signed-off-by: David Horstmann <david.horstmann@arm.com>
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Dehui Sun authored
add timer driver. Signed-off-by: Dehui Sun <dehui.sun@mediatek.com> Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7
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Nina Wu authored
Add system_reset function in psci ops Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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gtk_pangao authored
1.add sys_cirq driver 2.add gic api for cirq Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
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- 27 Oct, 2020 9 commits
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch is used to fix remaining non compliant code for Intel SoCFPGA's mailbox and sip driver. These changes include: - Change non-interface required uint32_t into unsigned int - Change non-negative variable to unsigned int - Remove obsolete variable initialization to 0 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch is used to fix remaining non compliant code for Intel SocFPGA's mailbox driver. These changes include: - adding integer literal for unsigned constant - fix non-boolean controlling expression - add braces even on conditional single statement bodies Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1
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Chee Hong Ang authored
Attempt to restart the mailbox if the mailbox driver not able to write any data into the mailbox command buffer. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: Ia45291c985844dec9da82839cac701347534d32b
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Abdul Halim, Muhammad Hadi Asyrafi authored
Allow mailbox command that is larger than mailbox command FIFO buffer size to be sent to SDM in multiple chunks. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26
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Abdul Halim, Muhammad Hadi Asyrafi authored
Change the main loop inside mailbox poll function from while(1) to a retry counter named sdm_loop. This is to limit the maximum possible looping of the function and prevent unexpected behaviour. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d
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Chee Hong Ang authored
For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b
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Chee Hong Ang authored
Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5
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Abdul Halim, Muhammad Hadi Asyrafi authored
This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2
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- 26 Oct, 2020 1 commit
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Po Xu authored
add GPIO driver Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd Signed-off-by: Po Xu <jg_poxu@mediatek.com>
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- 24 Oct, 2020 6 commits
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Abdul Halim, Muhammad Hadi Asyrafi authored
Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856
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Abdul Halim, Muhammad Hadi Asyrafi authored
Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402
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Chee Hong Ang authored
Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a
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Richard Gong authored
Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c
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Abdul Halim, Muhammad Hadi Asyrafi authored
Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319
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Abdul Halim, Muhammad Hadi Asyrafi authored
Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e
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- 21 Oct, 2020 4 commits
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Olivier Deprez authored
For the first partition, mark first 2GB as device memory excluding the Trusted DRAM region reserved for the SPMC. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b
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Tomas Pilar authored
The qemu_sbsa platform uses 42bit address size but the cortex-a53 only supports 40bit addressing, the cpu is incompatible with the platform. The aem_generic is also not used with qemu_sbsa, in fact, the platform currently only properly supports the cortex-a57 cpu. Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14 Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
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Pali Rohár authored
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6
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Fengquan Chen authored
add timer driver. Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com> Change-Id: I60a7273f922233a618a6163b802c0858ed89f75f
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- 20 Oct, 2020 2 commits
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Usama Arif authored
This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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Arunachalam Ganapathy authored
This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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