1. 19 Mar, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra186: disable PROGRAMMABLE_RESET_ADDRESS · 8336c94d
      Varun Wadekar authored
      
      
      This patch disables the code to program reset vector for secondary
      CPUs to a different entry point, than cold boot. The cold boot entry
      point has the ability to differentiate between a cold boot and a warm
      boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
      reusing the same entry point, we can lock the CPU reset vector during
      cold boot.
      
      Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8336c94d
  2. 11 Mar, 2020 1 commit
    • Pritesh Raithatha's avatar
      Tegra: smmu: remove context save sequence · a391d494
      Pritesh Raithatha authored
      
      
      SMMU and MC registers are saved as part of the System Suspend sequence.
      The register list includes some NS world SMMU registers that need to be
      saved by NS world software instead. All that remains as a result are
      the MC registers.
      
      This patch moves code to MC file as a result and renames all the
      variables and defines to use the MC prefix instead of SMMU. The
      Tegra186 and Tegra194 platform ports are updated to provide the MC
      context register list to the parent driver. The memory required for
      context save is reduced due to removal of the SMMU registers.
      
      Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
      Signed-off-by: default avatarPritesh Raithatha <praithatha@nvidia.com>
      a391d494
  3. 23 Jan, 2019 3 commits