- 01 Jun, 2020 1 commit
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Jimmy Brisson authored
This should allow git to easily track file moves Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327
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- 30 May, 2020 1 commit
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joanna.farley authored
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- 29 May, 2020 1 commit
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Sandrine Bailleux authored
As per the trustedfirmware.org Project Maintenance Process [1], the current maintainers of the TF-A project have nominated some contributors to become maintainers themselves. List them in the maintainers.rst file to make this official. [1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ Change-Id: Id4e3cfd12a9074f4e255087fa5dd6fa5f902845f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 28 May, 2020 9 commits
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Mark Dykes authored
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Mark Dykes authored
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Mark Dykes authored
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Mark Dykes authored
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Mark Dykes authored
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joanna.farley authored
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Sandrine Bailleux authored
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Sandrine Bailleux authored
Extend the list of modules and assign code owners to each of them. Change-Id: I267b87d8e239c7eff143b4c7e6ce9712fcf7101e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Olivier Deprez authored
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- 27 May, 2020 7 commits
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Mark Dykes authored
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Mark Dykes authored
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Mark Dykes authored
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Manish Pandey authored
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Usama Arif authored
This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com>
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Manish V Badarkhe authored
Fixed build error for dualroot chain of trust. Build error were thrown as below while compiling the code for dualroot chain of trust: aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o: (.bss.auth_img_flags+0x0): multiple definition of `auth_img_flags'; ./build/fvp/debug/bl1/cot.o:(.bss.auth_img_flags+0x0): first defined here aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o: (.rodata.cot_desc_size+0x0): multiple definition of `cot_desc_size'; ./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_size+0x0): first defined here aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o: (.rodata.cot_desc_ptr+0x0): multiple definition of `cot_desc_ptr'; ./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_ptr+0x0): first defined here Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I1a426c4e7f5f8013d71dafc176c7467c1b329757
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Sandrine Bailleux authored
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- 26 May, 2020 6 commits
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Mark Dykes authored
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Alexei Fedorov authored
This patch fixes wrong ID_AA64DFR0_EL1 register read instead of ID_AA64PFR0_EL1 to detect support for MPAM extension. It also implements get_mpam_version() function which returns MPAM version as: 0x00: None Armv8.0 or later; 0x01: v0.1 Armv8.4 or later; 0x10: v1.0 Armv8.2 or later; 0x11: v1.1 Armv8.4 or later; Change-Id: I31d776b1a1b60cb16e5e62296d70adb129d7b760 Reported-by: Matteo Zini <matteozini96@gmail.com> Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Mark Dykes authored
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Olivier Deprez authored
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Olivier Deprez authored
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Sandrine Bailleux authored
Document the second argument of the function. Minor rewording. Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 25 May, 2020 2 commits
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Louis Mayencourt authored
- Fix possible run-time ELs value and xlat-granule size. - Remove mandatory field for stream-ids. - Define interrupts attributes to <u32>. - Remove mem-manage field. - Add description for memory/device region attributes. Co-authored-by: Manish Pandey <manish.pandey2@arm.com> Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I71cf4406c78eaf894fa6532f83467a6f4110b344
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J-Alves authored
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code). Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760 Signed-off-by: J-Alves <joao.alves@arm.com>
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- 22 May, 2020 2 commits
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Mark Dykes authored
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Jacky Bai authored
Add imx8mn basic support Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d
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- 21 May, 2020 7 commits
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Mark Dykes authored
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Mark Dykes authored
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Mark Dykes authored
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Manish Pandey authored
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Mark Dykes authored
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Madhukar Pappireddy authored
We query the UART base address and clk frequency in runtime using fconf getter APIs. Change-Id: I5f4e84953be5f384472bf90720b706d45cb86260 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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Madhukar Pappireddy authored
This patch introduces the populate function which leverages a new driver to extract base address and clk frequency properties of the uart serial node from HW_CONFIG device tree. This patch also introduces fdt helper API fdtw_translate_address() which helps in performing address translation. Change-Id: I053628065ebddbde0c9cb3aa93d838619f502ee3 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 20 May, 2020 4 commits
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Mark Dykes authored
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Varun Wadekar authored
This patch enables SDEI support for all Tegra platforms, with the following configuration settings. * SGI 8 as the source IRQ * Special Private Event 0 * Three private, dynamic events * Three shared, dynamic events * Twelve general purpose explicit events Verified using TFTF SDEI test suite. ******************************* Summary ******************************* Test suite 'SDEI' Passed ================================= Tests Skipped : 0 Tests Passed : 5 Tests Failed : 0 Tests Crashed : 0 Total tests : 5 ================================= Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
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Mark Dykes authored
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Sandrine Bailleux authored
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