GitLab

Update to support new part numbers.

Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F,
STM32MP151D, STM32MP153D, STM32MP157D

The STM32MP1 series is available in 3 different lines which are pin-to-pin
compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
              3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz
              and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz

Each line comes with a security option (cryptography & secure boot)
& a Cortex-A frequency option :

- A      Basic + Cortex-A7 @ 650 MHz
- C      Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D      Basic + Cortex-A7 @ 800 MHz
- F      Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz

Remove useless variable in stm32mp_is_single_core().

Change-Id: Id30c836af986c6340c91efa8a7ae9480a2827089
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add a new revision of STM32MP15x CPU (Rev.Z).

Change-Id: I227dd6d9b3fcc43270015cfb21f60aeb0a8ab658
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

* changes:
  Makefile: Remove unused macro
  plat: brcm: Remove 'AARCH32' deprecated macro
  Remove deprecated macro from TF-A code

Removed unused macro AARCH32 and AARCH64 from makefile

Change-Id: I6729e300f18d66dd7c6978d3bbd5a88937839c31
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Removed 'AARCH32' deprecated macro from 'stingray'
Broadcom platform code.

Change-Id: If8d9e785b7980fefd39df06547fcf71b899fd735
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Removed '__ASSEMBLY__' deprecated macro from TF-A code

Change-Id: I9082a568b695acb5b903f509db11c8672b62d9d0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

This patch adds default value of 'sha256' for HASH_ALG
build flag to 'make_helpers\defaults.mk', according to
'docs\getting_started\build-options.rst'.
This fixes Measured Boot driver error when TF-A uses
default HASH_ALG value and TPM_HASH_ALG is set to
sha384 or sha512.

Change-Id: Id0aa34b54807de0adaf88e5f7d7032577c22f365
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

In the function gicv2_set_spi_routing, the signed value proc_num is cast
to unsigned int before being compared to other unsigned values in two
assert calls.  The value proc_num can be a negative value, and once the
negative value is cast to unsigned it becomes a very large number which
will trigger the assert.  This patch changes the assert cast so that the
unsigned values are cast to signed instead, keeping the same functionality
but allowing proc_num to be negative.

This bug can be seen when running the SDEI RM_ANY routing mode test in
TFTF on the Juno platform.

This patch also makes the usage of the proc_num variable in other gicv2
functions more clear.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If1b98eebb00bd9b73862e5e995e5e68c168170a6

* changes:
  lib/cpus: update MIDR value for rainier cpu
  fdts: enable virtio-rng component for morello fvp platform

This patch updates the MIDR value for rainier cpu.

Change-Id: I99a5d96f757239cf65b2688095c4ec66cd991cf9
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>

* changes:
  stm32mp1: cosmetics in platform.mk
  stm32mp1: update rules for stm32image tool
  stm32mp1: add macros to define PLAT_PARTITION_MAX_ENTRIES
  stm32mp1: sort platform.mk
  stm32mp1: use ASFLAGS for binary paths
  stm32mp1: use internal MAKE_LD macro to generate stm32 linker files

Remove some useless extra tabs or spaces.
Replace some spaces with tabs.

Change-Id: I0e8e2a1a1be7a1109ba7f3e3ae35e3fe1b5b4552
Signed-off-by: Yann Gautier <yann.gautier@st.com>

In heavy parallel builds, it has sometimes been seen issues with the
tool not generated before it was needed. Change some rules order and
dependency to solve that.

Change-Id: I8f4b4f46a2ea0fe496bc66bca47c66d1c81d3c99
Signed-off-by: Yann Gautier <yann.gautier@st.com>

There were fixed values when computing PLAT_PARTITION_MAX_ENTRIES.
Use STM32_BL33_PARTS_NUM and STM32_RUNTIME_PARTS_NUM. The first one is
for the number of copies of BL33. The second one depends on the use case
SP_min or OP-TEE. For OP-TEE, there are 3 partitions. For SP_min, as it
is in the same binary as BL2, it is set to 0. It will be set to 1 if
BL32 is in a separate binary.

Change-Id: Iba4d8ec5fbc713bebfbdcd9f9426c3fded20d3ad
Signed-off-by: Yann Gautier <yann.gautier@st.com>

First put Makefile variables definition, then definitions for each feature,
then C flags, then source files, then compilation rules.

Change-Id: I238115ea2fe4ebafccd2135979814c27932c34e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

To simplify the rule that creates the concatenated binary, use ASFLAGS
instead of adding all paths in the AS command line. This allows a better
management if a binary is not present.

Change-Id: Ic8b4566e7dedc6f55be355a92e3b214cef138d9b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The previous proprietary version was not correctly handling dependencies.
Using MAKE_LD from make_helpers files now correctly handles that.
The generated linker script is the same as before.

Change-Id: Iccfd8dc3fffa7a33e73b184b72e0dfd5d26bc9c9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

enable virtio-rng component for morello fvp platform

Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>

Clear interrupt flag register after each sector read to avoid
issue when checking the register status.
Without clearing the interrupt, the status read doesn't wait
properly the ready bit.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: If290e3f165b986f0e736bb1b5e4d3dad4b749d74

Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core.  The workaround is to
set bit 8 in the ECTLR_EL1 register, there is a small performance cost
(<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9

Coverity raised an eyebrow over our GICR frame size calculation:
========
    CID 362942:  Integer handling issues  (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "nr_cores * gicr_frame_size" with type
"unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic,
and then used in a context that expects an expression of type "uint64_t"
(64 bits, unsigned).
========

Even with a GICv4 (256KB frame size) we need 16384 cores to overflow
32-bit, so it's not a practical issue.

But it's also easy to fix, so let's just do that: cast gicr_frame_size
to an unsigned 64-bit integer, so that the multiplication is done in the
64-bit realm.

Change-Id: Iad10e19b9e58d5fbf9d13205fbcef0aac5ae48af
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

* changes:
  Rename Neoverse Zeus to Neoverse V1
  Rename Cortex Hercules AE to Cortex 78 AE

Only define arm_get_rotpk_info_regs if ROTPK is in registers,
i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will
allow platform build without definition of TZ_PUB_KEY_HASH_BASE
if dedicated registers for ROTPK are not available on the platform.

Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7
Signed-off-by: Usama Arif <usama.arif@arm.com>

* changes:
  docs: marvell: update mv_ddr branch
  plat: marvell: armada: a3k: rename the UART images archive
  plat: marvell: armada: a3k: allow image load to RAM address 0
  marvell: comphy: cp110: add support for USB comphy polarity invert
  marvell: comphy: cp110: add support for SATA comphy polarity invert
  marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
  drivers: marvell: mochi: Update AP incoming masters secure level
  plat: marvell: armada: add ccu window for workaround errata-id 3033912
  plat: marvell: ap806: implement workaround for errata-id FE-4265711

Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.

Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot output folder upon flash image build.

Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.

Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>