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ERRATA_A57_829520 disables "indirect branch prediction" for
EL1 on cpu reset, leading to 15% drop in CPU performance
with coremark benchmarks.

Tegra210 already has a hardware fix for ARM BUG#829520,so
this errata is not needed.

This patch disables the errata to get increased performance
numbers.

Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20
Signed-off-by: Mithun Maragiri <mmaragiri@nvidia.com>

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2fbd2483d51fd28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch dynamically maps the first page of trusty's code memory,
before accessing it to find out if we are running a 32-bit or 64-bit
image.

On Tegra platforms, this means we have to increase the mappings to
accomodate the new memmap entry.

Change-Id: If370d1e6cfcccd69b260134c1b462d8d17bee03d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.

Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.

The CPU initates the cluster idle sequence on the last standing
CPU, by following these steps:

Entry
-----
* stop other CPUs from waking up
* program the PWM pinmux to tristate for OVR PMIC
* program the flow controller to enter CC6 state
* skip L1 $ flush during cluster power down, as L2 $ is inclusive
  of L1 $ on Cortex-A57 CPUs

Exit
----
* program the PWM pinmux to un-tristate for OVR PMIC
* allow other CPUs to wake up

This patch also makes sure that cluster idle state entry is not
enabled until CL-DVFS is ready.

Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.

Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.

Change-Id: I7506562bfac78421a80fb6782ac8472fbef6cfb0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. This takes care of scenarios when we get multiple
requests to memmap memory apertures at the same time.

Change-Id: If4fe23b454e7d588e35acfbf024b9ccbb3daccc7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates the macros to include the newly added IRAM
memory apertures.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I931daa310d738e8bf966f14e11d0631920e9bdde

This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power states. The Tegra210 platform port queries the BPMP
to calculate the target state for the cluster. In case BPMP does not
allow CCx entry, the core enters a power down state.

Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.

Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch converts Tegra platforms to support native
GICv2 drivers. This involves removes Tegra's GIC driver
port platforms to use interrupt_props

Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/



Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by
erratum 855873.

Enable the workaround that TF provides to fix this erratum.

Change-Id: I6cef4ac60ae745e9ce299ee22c93b9d2c4f6c5f2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

This patch enables the following erratas for the Tegra210 SoC:

* Cortex-A57
=============
- A57_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A57_826974
- ERRATA_A57_826977
- ERRATA_A57_828024
- ERRATA_A57_829520
- ERRATA_A57_833471

* Cortex-A53
=============
- A53_DISABLE_NON_TEMPORAL_HINT
- ERRATA_A53_826319
- ERRATA_A53_836870

Tegra210 uses Cortex-A57 revision: r1p1 and Cortex-A53 revision: r0p2.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch modifies the TZDRAM base address to the new aperture
allocated by the bootloader.

Change-Id: Id158d15b1ec9aa681136d258e90fbba930aebf92
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements a handler for common SiP calls. A weak
implementation for the SoC-specific handler has been provided
which can be overridden by SoCs to implement any custom SiP
calls.

Change-Id: I45122892a84ea35d7b44be0f35dc15f6bb95193e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.

This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.

Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch renames the current Memory Controller driver files to
"_v1". This is done to add a driver for the new Memory Controller
hardware (v2).

Change-Id: I668dbba42f6ee0db2f59a7103f0ae7e1d4684ecf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch enables the processor retention and L2/CPUECTLR read/write
access from the NS world only for Cortex-A57 CPUs on the Tegra SoCs.

Change-Id: I9941a67686ea149cb95d80716fa1d03645325445
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves these address translation helper macros to individual
Tegra SoC makefiles to provide more control.

Change-Id: Ieab53c457c73747bd0deb250459befb5b7b9363f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch converts the common SiP handler to SoC specific SiP
handler. T210 and T132 have different SiP SMCs and so it makes
sense to move the SiP handler to soc/t132 and soc/t210 folders.

Change-Id: Idfe48384d63641137d74a095432df4724986b241
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The Flow Controller hardware block is not present across all Tegra
SoCs, hence include the driver files from SoC specific makefiles.

T132/T210 are the SoCs which include this hardware block while future
SoCs have removed it.

Change-Id: Iaca25766a4fa51567293d10cf14dae968b0fae80
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers,
so that the core waits for 512 generic timer CNTVALUEB ticks before
entering retention state, after executing a WFI instruction.

This functionality is configurable and can be enabled for platforms
by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and
'ENABLE_CPU_DYNAMIC_RETENTION' flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only the required CPU files.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.

This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This major change pulls out the common functionality from the
FVP and Juno platform ports into the following categories:

*   (include/)plat/common. Common platform porting functionality that
typically may be used by all platforms.

*   (include/)plat/arm/common. Common platform porting functionality
that may be used by all ARM standard platforms. This includes all
ARM development platforms like FVP and Juno but may also include
non-ARM-owned platforms.

*   (include/)plat/arm/board/common. Common platform porting
functionality for ARM development platforms at the board
(off SoC) level.

*   (include/)plat/arm/css/common. Common platform porting
functionality at the ARM Compute SubSystem (CSS) level. Juno
is an example of a CSS-based platform.

*   (include/)plat/arm/soc/common. Common platform porting
functionality at the ARM SoC level, which is not already defined
at the ARM CSS level.

No guarantees are made about the backward compatibility of
functionality provided in (include/)plat/arm.

Also remove any unnecessary variation between the ARM development
platform ports, including:

*   Unify the way BL2 passes `bl31_params_t` to BL3-1. Use the
Juno implementation, which copies the information from BL2 memory
instead of expecting it to persist in shared memory.

*   Unify the TZC configuration. There is no need to add a region
for SCP in Juno; it's enough to simply not allow any access to
this reserved region. Also set region 0 to provide no access by
default instead of assuming this is the case.

*   Unify the number of memory map regions required for ARM
development platforms, although the actual ranges mapped for each
platform may be different. For the FVP port, this reduces the
mapped peripheral address space.

These latter changes will only be observed when the platform ports
are migrated to use the new common platform code in subsequent
patches.

Change-Id: Id9c269dd3dc6e74533d0e5116fdd826d53946dc8

TLK Dispatcher (tlkd) is based on the tspd and is the glue required
to run TLK as a Secure Payload with the Trusted Firmware.

Change-Id: I69e573d26d52342eb049feef773dd7d2a506f4ab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch introduces a framework which will allow CPUs to perform
implementation defined actions after a CPU reset, during a CPU or cluster power
down, and when a crash occurs. CPU specific reset handlers have been implemented
in this patch. Other handlers will be implemented in subsequent patches.

Also moved cpu_helpers.S to the new directory lib/cpus/aarch64/.

Change-Id: I1ca1bade4d101d11a898fb30fea2669f9b37b956

Remove all usage of the vpath keyword in makefiles as it was prone
to mistakes. Specify the relative paths to source files instead.

Also reorder source files in makefiles alphabetically.

Fixes ARM-software/tf-issues#121

Change-Id: Id15f60655444bae60e0e2165259efac71a50928b

Move almost all system include files to a logical sub-directory
under ./include. The only remaining system include directories
not under ./include are specific to the platform. Move the
corresponding source files to match the include directory
structure.

Also remove pm.h as it is no longer used.

Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3

bl1/aarch64/early_exceptions.S used to be re-used by BL2, BL3-1 and
BL3-2.  There was some early SMC handling code in there that was not
required by the other bootloader stages.  Therefore this patch
introduces an even simpler exception vector source file for BL2,
BL3-1 and BL3-2.

Fixes ARM-software/tf-issues#38

Change-Id: I0244b80e9930b0f8035156a0bf91cc3e9a8f995d

At present, the entry point for each BL image is specified via the
Makefiles and provided on the command line to the linker. When using a
link script the entry point should rather be specified via the ENTRY()
directive in the link script.

This patch updates linker scripts of all BL images to specify the entry
point using the ENTRY() directive. It also removes the --entry flag
passed to the linker through Makefile.

Fixes issue ARM-software/tf-issues#66

Change-Id: I1369493ebbacea31885b51185441f6b628cf8da0

This change requires all platforms to now specify a list of source files
rather than object files.

New source files should preferably be specified by using the path as
well and we should add this in the future for all files so we can remove
use of vpath. This is desirable because vpath hides issues like the fact
that BL2 currently pulls in a BL1 file bl1/aarch64/early_exceptions.S
and if in the future we added bl2/aarch64/early_exceptions.S then it's
likely only one of the two version would be used for both bootloaders.

This change also removes the 'dump' build target and simply gets
bootloaders to always generate a dump file. At the same time the -x
option is added so the section headers and symbols table are listed.

Fixes ARM-software/tf-issues#11

Change-Id: Ie38f7be76fed95756c8576cf3f3ea3b7015a18dc
Signed-off-by: Jon Medhurst <tixy@linaro.org>

This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.

A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.

This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.

Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6

Tidy up the spacing of variable definitions within the makefiles to make
them more consistent, easier to read and amend.

Change-Id: Ic6d7c8489ca4330824abb5cd1ead8f1d449d1a85
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

Move all explicit platform or architecture specific references
into a new platform.mk file that is defined for each platform.

Change-Id: I9d6320d1ba957e0cc8d9b316b3578132331fa428
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>