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Ensure PMF service timestamps are properly aligned on a cache line bo…

Rename `pmf_calc_timestamp_offset` to `pmf_calc_timestamp_addr`

GICv3: Allow either G1S or G0 interrupts to be configured

Support for PSCI NODE_HW_STATE

fiptool: Add support for printing the sha256 digest with info command

xilinx: ZynqMP updates
- new SIP calls for bitstream programming
- new SIP call to discover the SOC silicon version
- support the delay timer

This patch implements CSS platform hook to support NODE_HW_STATE PSCI
API. The platform hook queries SCP to obtain CSS power state. Power
states returned by SCP are then converted to expected PSCI return codes.

Juno's PSCI operation structure is modified to use the CSS
implementation.

Change-Id: I4a5edac0e5895dd77b51398cbd78f934831dafc0

This patch adds the function scpi_get_css_power_state to perform the
'Get CSS Power State' SCP command and handle its response. The function
parses SCP response to obtain power states of requested cluster and CPUs
within.

Change-Id: I3ea26e48dff1a139da73f6c1e0893f21accaf9f0

This patch implements FVP platform hook to support NODE_HW_STATE PSCI
API. The platform hook validates the given MPIDR and reads corresponding
status from FVP power controller, and returns expected values for the
PSCI call.

Change-Id: I286c92637da11858db2c8aba8ba079389032de6d

This patch adds support for NODE_HW_STATE PSCI API by introducing a new
PSCI platform hook (get_node_hw_state). The implementation validates
supplied arguments, and then invokes this platform-defined hook and
returns its result to the caller. PSCI capabilities are updated
accordingly.

Also updates porting and firmware design guides.

Change-Id: I808e55bdf0c157002a7c104b875779fe50a68a30

Restore some defines in xlat_tables.h

Add some missing forward declarations in plat_arm.h

This patch adds a couple of missing forward declarations in plat_arm.h
so that all types it references are known within this header file,
without relying on previous header inclusions. This concerns the
meminfo and bl31_params structures, which are defined in bl_common.h.
Other external types referenced from plat_arm.h (e.g. mmap_region_t)
get declared through header files included by arm_plat.h so they
don't need forward declarations.

Change-Id: I471d5aa487919aff3fa979fc65e053f4f5b0ef32

Commit e8719552 removed some definitions related to translation
tables from the xlat_tables.h header file, based on the assumption
that they weren't used by any platform. These are actually used by
some partners so this patch restores them.

Fixes ARM-software/tf-issues#425

Change-Id: Idafa5f00bb0bd9c2847b5ae6541cf8db93c7b89a

mediatek: Support for Mediatek MT6795 SoC

rockchip: Fixes typo and warnings

When using more than a single service in PMF, it is necessary that the
per-service timestamps begin on a cache line boundary.  Previously it
was possible that two services shared a cache line for their
timestamps.  This made it difficult to reason about cache maintenance
operations within a single service and required a global understanding
of how all services operate.

Change-Id: Iacaae5154a7e19ad4107468e56df9ad082ee371c

The macro calculates an absolute address rather than an offset so
rename it to avoid confusion.

Change-Id: I351f73dfd809fd28c0c30d38928caf5c5cd1af04

We must guarantee that writes have become effective before returning to
the caller. Hence, wait for PMUFW signaling completion of the FW call
before returning to the rich OS.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Add support to provide silicon id to non-secure
software through SMC.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

[ sb
Move zynqmp_get_silicon_id outside of compile guards to avoid build
errors.
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide
the Access to the xilfpga library to load the bitstream into zynqmp
PL region.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>

This patch adds a new pm ID to sync with PMUFW ID numbers.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

During system suspend, identify slaves which are configured
as wake sources and call pm_set_wakeup_source API for each of them.

Identifying if device may wake the system is done by checking if any
interrupt of that device is enabled in GICD_ISENABLER when the APU is
about to enter SUSPEND_TO_RAM state. If such interrupt is found,
pm_set_wakeup_source is called with corresponding PM node ID as
argument.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>

The state argument of the pm_self_suspend API encodes the state to
which the APU intends to suspend. The state can be:
- PM_APU_STATE_CPU_IDLE - processor power down, all memories remain
  on
- PM_APU_STATE_SUSPEND_TO_RAM - all processors powered down, L2$
  powered down, all OCM banks in retention and DDR in
  self-refresh.
The calls for setting requirements for L2$ and OCM banks are now
redundant and removed.
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
[ sb
 - remove redundant #defines
]
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>

Implementation is based on arm_validate_power_state().
This function is called during CPU_SUSPEND PSCI call to validate
power_state parameter. If state is valid this function populate it
in req_state array as power domain level specific local state.
ATF platform migration guide chapter 2.2 defines this function as
mandatory for PSCIv1.0 CPU_SUSPEND support.
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>

When moving the ATF into the DRAM address space an additional
translation table is required.
Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

The OCM space was reorganized to use the space more efficiently. Adjust
the default ATF location to be aligned with other ZynqMP software
components.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Arm provided error injection support. To enable this error injection,
we need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in
CPUACTLR_EL1 register.

This is needed for our cortexa53 edac linux driver testing.
These registers need write access from non secure EL1 i.e linux
at the time of setting the above bits.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>

ZynqMP only supports builds with RESET_TO_BL31=1. Set this option
through the platform makefile on default.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Nodes represent IPI dedicated to the RPU (not accessible by APU)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>

Initialize the generic_delay_timer in the zynqmp port.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

rockchip: fixes the gic panic for rk3399 resume

We make sure the resuming of gic need to be enabled.
Otherwise, The resume will hit the below panic.
...
[   24.230541] CPU0: update max cpu_capacity 451
[   24.236029] CPU5: update max cpu_capacity 1024
[   24.236046] CPU4: shutdown
[   24.243205] psci: CPU4 killed.
[   24.258730] CPU5: shutdown
[   24.261472] psci: CPU5 killed.
[   24.270417] GIC: unable to set SRE (disabled at EL2), panic ahead
[   24.270417] cat[7801]: undefined instruction: pc=ffffffc0004e65d0
[   24.270417] Code: b0003940 91274400 97f871af d2801e00 (d5184600)
[   24.270417] Internal error: Oops - undefined instruction: 0 [#1] PREEMPT

Change-Id: Ie9542c8d5768ba0accfa073453da8bfe06d4f921

Set apio for rk3399

Currently the GICv3 driver mandates that platform populate
both G1S and G0 interrupts. However, it is possible that a
given platform is not interested in both the groups and
just needs to specify either one of them.

This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()`
functions to allow either G1S or G0 interrupts to be configured.

Fixes ARM-software/tf-issues#400

Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b

This feature allows one to quickly verify that the expected
image is contained in the FIP without extracting the image and
running sha256sum(1) on it.

The sha256 digest is only shown when the verbose flag is used.

This change requires libssl-dev to be installed in order to build
Trusted Firmware. Previously, libssl-dev was optionally needed only
to support Trusted Board Boot configurations.

Fixes ARM-Software/tf-issues#124

Change-Id: Ifb1408d17f483d482bb270a589ee74add25ec5a6

This patch support single core to boot to Linux kernel
through Trusted Firmware.
It also support 32 bit kernel and 64 bit kernel booting.

Flush `psci_plat_pm_ops` after initialization