- 23 Nov, 2018 1 commit
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Sathees Balya authored
This patch adds support to build a combined BL1 and ROMLIB binary file with the right page alignment in Juno. When USE_ROMLIB=1 is set for Juno, it generates the combined file bl1_romlib.bin which needs to be used instead of bl1.bin Change-Id: I407efbe48d3e522fa6ef855538a9587193cb1919 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Nov, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 01 Nov, 2018 2 commits
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Sudeep Holla authored
When CSS_USE_SCMI_DRIVER is not defined or set to 0, we get the following build error. plat/arm/board/juno/juno_topology.c:16:19: error: ‘CSS_SCMI_PAYLOAD_BASE’ undeclared here (not in a function) .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, ^~~~~~~~~~~~~~~~~~~~~ plat/arm/board/juno/juno_topology.c:17:38: error: ‘CSS_SCMI_MHU_DB_REG_OFF’ undeclared here (not in a function) .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, ^~~~~~~~~~~~~~~~~~~~~~~ CSS_CPU_PWR_STATE_OFF Fix the error in order to get function legacy SCPI support functional. Change-Id: I00cb80db9968aa0be546e33a3a682a2db87719be Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Antonio Nino Diaz authored
Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 26 Oct, 2018 1 commit
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Roberto Vargas authored
This function is not related to Arm platforms and can be reused by other platforms if needed. Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Version 1.4.7 of libfdt is bigger than the current one (1.4.2) and the current reserved space for BL2 in Juno isn't enough to fit the Trusted Firmware when compiling with clang or armclang. Change-Id: I7b73394ca60d17f417773f56dd5b3d54495a45a8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Oct, 2018 1 commit
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Chandni Cherukuri authored
The default values of 'plat_css_scmi_plat_info' is not applicable for all the platforms. There should be a provision to let platform code to register a platform specific instance of scmi_channel_plat_info_t. Add a new API 'plat_css_get_scmi_info' which lets the platform to register a platform specific instance of scmi_channel_plat_info_t and remove the default values. In addition to this, the existing 'plat_css_scmi_plat_info' structure is removed from the common code and instantiated for the platforms that need it. This allows for a consistent provisioning of the SCMI channel information across all the existing and upcoming platforms. Change-Id: I4fb65d7f2f165b78697b4677f1e8d81edebeac06 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 15 Oct, 2018 1 commit
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Deepak Pandey authored
macro jump_if_cpu_midr is used commonly by many arm platform. It has now been relocated to common place to remove duplication of code. Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
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- 11 Oct, 2018 3 commits
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Sathees Balya authored
Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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Antonio Nino Diaz authored
This file is shared between FVP and all CSS platforms. While it may be true that some definitions can be common, it doesn't make sense conceptually. For example, the stack size depends on the platform and so does the SRAM size. After removing them, there are not enough common definitions to justify having this header, so the other definitions have been moved to the platform_def.h of FVP, board_css_def.h and arm_def.h. Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This file is only used by Juno as all other CSS platforms have their own private memory maps. Change-Id: I1c9f27aac7b1d8bff4d92674e8bde5505b93c8c4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Oct, 2018 2 commits
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Antonio Nino Diaz authored
This way it can be reused by other platforms if needed. Note that this driver is designed to work with the Versatile Express NOR flash of Juno and FVP. In said platforms, the memory is organized as an interleaved memory of two chips with a 16 bit word. Any platform that wishes to reuse it with a different configuration will need to modify the driver so that it is more generic. Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Deepak Pandey authored
This lets any future CSS platforms to use RESET_TO_BL31 flag. Change-Id: I32a90fce43cb0c6f4d33589653a0fd6a7ecc9577 Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
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- 02 Oct, 2018 1 commit
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Antonio Nino Diaz authored
This option makes it hard to optimize the memory definitions of all Arm platforms because any change in the common defines must work in all of them. The best thing to do is to remove it and move the definition to each platform's header. FVP, SGI and SGM were using the definitions in board_arm_def.h. The definitions have been copied to each platform's platform_def.h. Juno was already using the ones in platform_def.h, so there have been no changes. Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Remove references to removed build options. - Remove support for legacy GIC driver. - Remove support for LOAD_IMAGE_V2=0. Change-Id: I72f8c05620bdf4a682765e6e53e2c04ca749a3d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Sep, 2018 1 commit
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Sathees Balya authored
The patch 7b56928a unified the FWU mechanism on FVP and Juno platforms due to issues with MCC firmware not preserving the NVFLAGS. With MCCv150 firmware, this issue is resolved. Also writing to the NOR flash while executing from the same flash in Bypass mode had some stability issues. Hence, since the MCC firmware issue is resolved, this patch reverts to the NVFLAGS mechanism to detect FWU. Also, with the introduction of SDS (Shared Data Structure) by the SCP, the reset syndrome needs to queried from the appropriate SDS field. Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554 Signed-off-by: Sathees Balya <sathees.balya@arm.com> Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>
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- 30 Aug, 2018 1 commit
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Daniel Boulby authored
Add another level of abstraction of weak defs for arm_bl2_handle_post_image_load to prevent two weak definitions of the same function Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 21 Aug, 2018 1 commit
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Roberto Vargas authored
All the arm platforms were including the files related to mem-protect. This configuration generates some problems with new platforms that don't support such functionality, and for that reason this patch moves these files to the platform specific makefiles. Change-Id: I6923e5224668b76667795d8e11723cede7979b1e Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 06 Aug, 2018 1 commit
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Roberto Vargas authored
Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 24 Jul, 2018 1 commit
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Jun, 2018 1 commit
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Roberto Vargas authored
Having these definitions in board_arm_def.h forces to all the arm platforms to use the same definition for PLAT_ARM_MEM_PROT_ADDR. This macro also enables the mem-protect mechanism, which means that all the arm platform has enabled mem-protect and they cannot get rid of it. Change-Id: Id29d2c51cbe6edc15f010a9f5a20c42266c48a08 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 07 Jun, 2018 2 commits
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Soby Mathew authored
This patch bumps up the BL1-RW size for Juno and at the same time reduces the BL2 size when TBB is enabled, TF_MBEDTLS_KEY_ALG=rsa+ecdsa. The BL2 size for this config is reduced as it was observed that the peak memory usage is only reached when SPD=opteed and the dual rsa+ecdsa support is not needed for this case. Change-Id: Ia9009771b5cfd805e9cc75410aabb7db99fc2fbc Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
The patch changes the layout of BL images in memory to enable more efficient use of available space. Previously BL31 was loaded with the expectation that BL2 memory would be reclaimed by BL32 loaded in SRAM. But with increasing memory requirements in the firmware, we can no longer fit BL32 in SRAM anymore which means the BL2 memory is not reclaimed by any runtime image. Positioning BL2 below BL1-RW and above BL31 means that the BL31 NOBITS can be overlaid on BL2 and BL1-RW. This patch also propogates the same memory layout to BL32 for AArch32 mode. The reset addresses for the following configurations are also changed : * When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode * When BL2_AT_EL3=1 for BL2 The restriction on BL31 to be only in DRAM when SPM is enabled is now removed with this change. The update to the firmware design guide for the BL memory layout is done in the following patch. Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 11 May, 2018 1 commit
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Chris Kay authored
SGI-575's NSRAM is neither in the same place nor the same size as Juno's. Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823 Signed-off-by: Chris Kay <chris.kay@arm.com>
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- 01 May, 2018 1 commit
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Roberto Vargas authored
Previously mem_protect used to be only supported from BL2. This is not helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates mem_protect from el3_runtime firmware on ARM Platforms specifically when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap tables temporarily and then the protected regions are then cleared. This avoids the need to map the non secure DRAM permanently to BL31/sp_min. The stack size is also increased, because DYNAMIC_XLAT_TABLES require a bigger stack. Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 10 Apr, 2018 2 commits
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Summer Qin authored
Add TZMP1 support on Juno and increase the BL2 size accordingly due to the extra data structures to describe the TZC regions and the additional code. Signed-off-by: Summer Qin <summer.qin@arm.com>
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Summer Qin authored
This patch allows the ARM Platforms to specify the TZC regions to be specified to the ARM TZC helpers in arm_tzc400.c and arm_tzc_dmc500.c. If the regions are not specified then the default TZC region will be configured by these helpers. This override mechanism allows specifying special regions for TZMP1 usecase. Signed-off-by: Summer Qin <summer.qin@arm.com>
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- 09 Apr, 2018 1 commit
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Amit Daniel Kachhap authored
Building TBBR(SPD=opteed) and non-TBBR TF-A images is breaking for Juno for different configurations listed below: * Overflow error of 4096 bytes for rsa algorithm. * Overflow error of 8192 bytes for ecdsa algorithm. * Overflow error of 4096 bytes for rsa+ecdsa algorithm. * Overflow error of 4096 bytes for non-TBBR case. So this patch increments macro PLAT_ARM_MAX_BL2_SIZE for all the above cases accordingly. Change-Id: I75ec6c0a718181d34553fe55437f0496f467683f Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
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- 08 Mar, 2018 1 commit
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Soby Mathew authored
Previously, Juno used to depend on the SSC_GPRETN register to inform about the reset syndrome. This method was removed when SCP migrated to the SDS framework. But even the SDS framework doesn't report the reset syndrome correctly and hence Juno failed to enter Firmware update mode if BL2 authentication failed. In addition to that, the error code populated in V2M_SYS_NVFLAGS register does not seem to be retained any more on Juno across resets. This could be down to the motherboard firmware not doing the necessary to preserve the value. Hence this patch modifies the Juno platform to use the same mechanism to trigger firmware update as FVP which is to corrupt the FIP TOC on authentication failure. The implementation in `fvp_err.c` is made common for ARM platforms and is moved to the new `arm_err.c` file in plat/arm/common folder. The BL1 and BL2 mmap table entries for Juno are modified to allow write to the Flash memory address. Change-Id: Ica7d49a3e8a46a90efd4cf340f19fda3b549e945 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 28 Feb, 2018 2 commits
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Roberto Vargas authored
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=juno LOG_LEVEL=50 all Change-Id: Ic8f611da734f356566e8208053296e6c62b54709 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Sandrine Bailleux authored
The SCP binaries provided in the 17.10 Linaro release (and onwards) have migrated to the SCMI/SDS protocols. Therefore, the ARM TF should now use the corresponding drivers by default. This patch changes the default value of the CSS_USE_SCMI_SDS_DRIVER build option to 1 for Juno. Change-Id: Idb7e3c6af582f49e332167a2158703c2d781b437 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 26 Feb, 2018 1 commit
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Soby Mathew authored
The patch adds the necessary changes to load HW_CONFIG in BL2 for ARM Platforms : 1. The load address of HW_CONFIG is specified via the `hw_config_addr` property in TB_FW_CONFIG is loaded by BL1. The `hw_config_max_size` property defines the maximum size to be expected for the HW_CONFIG. The `arm_dyn_cfg_helpers.c` and corresponding header implements utility functions to parse these DT properties defined. The `arm_dyn_cfg.c` implements wrappers to these helpers to enable them to be invoked from ARM platform layer. 2. `HW_CONFIG` is added to the `bl2_mem_params_descs[]` array which is the list of images to be loaded by BL2. 3. The `libfdt` sources are now included when BL2 is built 4. A new helper `populate_next_bl_params_config()` is introduced in desc_image_load.c to populate the subsequent executable BL images with the `hw_config` and the corresponding `fw_config` if available. The `plat_get_next_bl_params()` API for ARM platforms is modified to invoke this new helper. 5. The implementation of `bl2_early_platform_setup2()` is modified to consider `arg0` as well in addition to `arg1` passed from BL1. 6. Bump up the BL2 size for Juno to accommodate the inclusion of libfdt. Change-Id: I80f1554adec41753e0d179a5237364f04fe13a3f Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 19 Dec, 2017 1 commit
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Jeenu Viswambharan authored
With this patch, ARM platforms are expected to define the macros PLAT_ARM_SDEI_PRIVATE_EVENTS and PLAT_ARM_SDEI_SHARED_EVENTS as a list of private and shared events, respectively. This allows for individual platforms to define their own events. Change-Id: I66851fdcbff83fd9568c2777ade9eb12df284b49 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 30 Nov, 2017 1 commit
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David Cunado authored
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero. This has a minor performance improvement with no functional impact. Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 29 Nov, 2017 2 commits
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Soby Mathew authored
The bl2_early_platform_setup() and bl2_platform_setup() were redefined for Juno AArch32 eventhough CSS platform layer had same definition for them. The CSS definitions definitions were previously restricted to EL3_PAYLOAD_BASE builds and this is now modified to include the Juno AArch32 builds as well thus allowing us to remove the duplicate definitions in Juno platform layer. Change-Id: Ibd1d8c1428cc1d51ac0ba90f19f5208ff3278ab5 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch fixes a couple of issues for AArch32 builds on ARM reference platforms : 1. The arm_def.h previously defined the same BL32_BASE value for AArch64 and AArch32 build. Since BL31 is not present in AArch32 mode, this meant that the BL31 memory is empty when built for AArch32. Hence this patch allocates BL32 to the memory region occupied by BL31 for AArch32 builds. As a side-effect of this change, the ARM_TSP_RAM_LOCATION macro cannot be used to control the load address of BL32 in AArch32 mode which was never the intention of the macro anyway. 2. A static assert is added to sp_min linker script to check that the progbits are within the bounds expected when overlaid with other images. 3. Fix specifying `SPD` when building Juno for AArch32 mode. Due to the quirks involved when building Juno for AArch32 mode, the build option SPD needed to specifed. This patch corrects this and also updates the documentation in the user-guide. 4. Exclude BL31 from the build and FIP when building Juno for AArch32 mode. As a result the previous assumption that BL31 must be always present is removed and the certificates for BL31 is only generated if `NEED_BL31` is defined. Change-Id: I1c39bbc0abd2be8fbe9f2dea2e9cb4e3e3e436a8 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 25 Oct, 2017 1 commit
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Qixiang Xu authored
For Trusted Board Boot, BL2 needs more space to support the ECDSA and ECDSA+RSA algorithms. Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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- 16 Oct, 2017 1 commit
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Jeenu Viswambharan authored
An earlier patch added provision for the platform to provide secure interrupt properties. ARM platforms already has a list of interrupts that fall into different secure groups. This patch defines macros that enumerate interrupt properties in the same fashion, and points the driver driver data to a list of interrupt properties rather than list of secure interrupts on ARM platforms. The deprecated interrupt list definitions are however retained to support legacy builds. Configuration applied to individual interrupts remain unchanged, so no runtime behaviour change expected. NOTE: Platforms that use the arm/common function plat_arm_gic_driver_init() must replace their PLAT_ARM_G1S_IRQS and PLAT_ARM_G0_IRQS macro definitions with PLAT_ARM_G1S_IRQ_PROPS and PLAT_ARM_G0_IRQ_PROPS macros respectively, using the provided INTR_PROP_DESC macro. Change-Id: I24d643b83e3333753a3ba97d4b6fb71e16bb0952 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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