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* changes:
  Fix boot failures on some builds linked with ld.lld.
  trusty: generic-arm64-smcall: Support gicr address
  trusty: Allow gic base to be specified with GICD_BASE
  trusty: Allow getting trusty memsize from BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE
  Fix clang build if CC is not in the path.

* changes:
  uniphier: make I/O register region configurable
  uniphier: make PSCI related base address configurable
  uniphier: make counter control base address configurable
  uniphier: make UART base address configurable
  uniphier: make pinmon base address configurable
  uniphier: make NAND controller base address configurable
  uniphier: make eMMC controller base address configurable

DynamIQ based designs have upto 8 CPUs in each cluster. This
patch fixes the device tree node which describes the topology
of the CPU for DynamIQ FVP Model.

Change-Id: I7146bc79029ce38314026d4853e5b6406863725c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Adding support for generating a semi-random number required for
enabling building TF-A with stack protector support.
TF-A for corstone-700 may now be built using ENABLE_STACK_PROTECTOR=all

Change-Id: I03e1be1a8d4e4a822cf286f3b9ad4da4337ca765
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

* changes:
  uniphier: extend boot device detection for future SoCs
  uniphier: change block_addressing flag to bool
  uniphier: change the return value type of .is_usb_boot() to bool

Pad the .rodata section to 16 bytes as ld.lld does not apply the ALIGN
statement on the .data section to the LMA. Fixes boot failure on builds
where the .rodata section happens to not be 16 bytes aligned.

Change-Id: I4e95678f73d8b326c5fc749dc7d0ce84e2d603f5
Signed-off-by: Arve Hjønnevåg <arve@android.com>

Add SMC_GET_GIC_BASE_GICR option to SMC_FC_GET_REG_BASE and
SMC_FC64_GET_REG_BASE calls for returning the base address of the gic
redistributor added in gic version 3.

Bug: 122357256
Change-Id: Ia7c287040656515bab262588163e0c5fc8f13a21
Signed-off-by: Arve Hjønnevåg <arve@android.com>

Some platforms define GICD_BASE instead of PLAT_ARM_GICD_BASE but the
meaning is the same.

Change-Id: I1bb04bb49fdab055b365b1d70a4d48d2058e49df
Signed-off-by: Arve Hjønnevåg <arve@android.com>

Some platforms define BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE, but
the meaning is the same.

Change-Id: I93d96dca442e653435cae6a165b1955efe2d2b75
Signed-off-by: Arve Hjønnevåg <arve@android.com>

If CC points to clang the linker was set to ld.lld. Copy the diectory
name from CC is it has one.

Change-Id: I50aef5dddee4d2540b12b6d4e68068ad004446f7
Signed-off-by: Arve Hjønnevåg <arve@android.com>

* changes:
  plat: marvell: armada: scp_bl2: allow loading up to 8 images
  plat: marvell: armada: add support for loading MG CM3 images

Change-Id: I011256ca60672a00b711c3f5725211be64bbc2b2
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8c2e6dc98f2f30a81f4f80cc0ca1232fed7a53c9

The I/O register region will be changed in the next SoC. Make it
configurable.

Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The next SoC will have:
  - No boot swap
  - SD boot
  - No USB boot

Add new fields to handle this.

Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The register base address will be changed in the next SoC. Make it
configurable.

Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The flag, uniphier_emmc_block_addressing, is boolean logic, so
"bool' is more suitable.

uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0
depending on the card density, or a negative value on failure.
Rename it to make it less confusing.

Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

This is boolean logic, so "bool" is more suitable.

Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The next SoC supports the same UART, but the register base will be
changed. Make it configurable.

Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The register base will be changed in the next SoC. Make it
configurable.

Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The next SoC does not support the NAND controller, but make the base
address configurable for consistency and future proof.

Change-Id: I776e43ff2b0408577919b0b72849c3e1e5ce0758
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The next SoC supports the same eMMC controller, but the register
base will be changed. Make it configurable.

Change-Id: I00cb5531bc3d8d49357ad5e922cdd3d785355edf
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

* changes:
  arm-io: Panic in case of io setup failure
  MISRA fix: Use boolean essential type
  fconf: Add documentation
  fconf: Move platform io policies into fconf
  fconf: Add mbedtls shared heap as property
  fconf: Add TBBR disable_authentication property
  fconf: Add dynamic config DTBs info as property
  fconf: Populate properties from dtb during bl2 setup
  fconf: Load config dtb from bl1
  fconf: initial commit

Forced hash generation used to always generate hash via RSA encryption.
This patch changes encryption based on ARM_ROTPK_LOCATION.
Also removes setting KEY_ALG based on ARM_ROTPL_LOCATION - there is no
relation between these two.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Id727d2ed06176a243719fd0adfa0cae26c325005

* changes:
  SPMD: enable SPM dispatcher support
  SPMD: hook SPMD into standard services framework
  SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
  SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP
  SPMD: add support for an example SPM core manifest
  SPMD: add SPCI Beta 0 specification header file

* changes:
  amlogic: axg: Add a build flag when using ATOS as BL32
  amlogic: axg: Add support for the A113D (AXG) platform

This patch adds support to the build system to include support for the SPM
dispatcher when the SPD configuration option is spmd.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: Ic1ae50ecd7403fcbcf1d318abdbd6ebdc642f732

This patch adds support to initialise the SPM dispatcher as a standard
secure service. It also registers a handler for SPCI SMCs exported by
the SPM dispatcher.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I2183adf826d08ff3fee9aee75f021021162b6477

This patch adds a rudimentary SPM dispatcher component in EL3.
It does the following:

- Consumes the TOS_FW_CONFIG to determine properties of the SPM core
  component
- Initialises the SPM core component which resides in the BL32 image
- Implements a handler for SPCI calls from either security state. Some
  basic validation is done for each call but in most cases it is simply
  forwarded as-is to the "other" security state.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I7d116814557f7255f4f4ebb797d1619d4fbab590