- 18 Aug, 2020 1 commit
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Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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- 03 Jun, 2020 1 commit
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Masahisa Kojima authored
64KB was not enouth to handle fdt, bl2 shows following error message. "ERROR: Invalid Device Tree at 0x10000000000: error -3" This patch increases the size to 1MB to address above error. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I0726a0cea95087175451da0dba7410acd27df808
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- 24 Jan, 2020 1 commit
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259
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- 01 Oct, 2019 2 commits
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Radoslaw Biernacki authored
This patch adds mapping for secure FLASH0 for qemu/virt and qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both platforms share common code, changes in common defines was necessary. For qemu_sbsa, this patch adds necessary mapping in order to boot without semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with variables) since it need to "run in place" in non secure domain. Changes for this are under RFC at edk2-platforms mailing list: https://patches.linaro.org/patch/171327/ (edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc). In docs qemu/virt is described as using semi-hosting, therefore this change should be orthogonal to existing assumptions while giving possibility to store both bl1 and fip in FLASH0 at some point (additional changes required for that). Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
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Radoslaw Biernacki authored
This patch introduces Qemu SBSA platform. Both platform specific files where copied from qemu/qemu with changes for DRAM base above 32bit and removal of ARMv7 conditional defines/code. Documentation is aligned to rest of SBSA patches along the series and planed changes in edk2-platform repo. Fixes ARM-software/tf-issues#602 Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I8ebc34eedb2268365e479ef05654b2df1b99128c
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- 18 Sep, 2019 2 commits
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Radoslaw Biernacki authored
Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size calculation. Use of additional parenthesis removes the possibility of improper calculations due nested macro expansion for subtraction. In case of platforms with DRAM window over 32bits, patch also removes potential problems with type casting, as meminfo.image_size is uint32_t but macro calculations were done in 64bit space. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018
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Radoslaw Biernacki authored
This commit change the plat/qemu directory structure into: `-- plat `-- qemu |-- common (files shared with all qemu subplatforms) |-- qemu (original qemu platform) |-- qemu_sbsa (new sqemu_sbsa platform) |-- subplat1 `-- subplat2 This opens the possibility of adding new qemu sub-platforms which reuse existing common platform code. The first platform which will leverage new structure will be SBSA platform. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b
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- 26 Jul, 2019 2 commits
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Hongbo Zhang authored
This patch adds gicv3 support for qemu, in order not to break any legacy use case, gicv2 is still set by default, gicv3 can be selected by compiling parameter QEMU_USE_GIC_DRIVER=QEMU_GICV3. Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org> Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: Ic63f38abf16ed3c36aa60e80d50103cf05cf797b
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Hongbo Zhang authored
This file moves gicv2 codes to a new separate files, target is to add gicv3 support later. Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org> Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Oct, 2018 1 commit
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Jerome Forissier authored
Since upstream QEMU commit 14ec3cbd7c1e ("device_tree: Increase FDT_MAX_SIZE to 1 MiB"), which is included in release v2.12.1 and later, BL2 initialization fails with the following error (-3 is -FDT_ERR_NOSPACE): ERROR: Invalid Device Tree at 0x40000000: error -3 Increase PLAT_QEMU_DT_MAX_SIZE accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Mar, 2018 1 commit
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Michalis Pappas authored
Allow qemu users to enable stack protection. Since the virt platform does not provide an RNG, use a basic, timer-based, canary generation, similarly to FVP. Increase SRAM size and BL2 size to fit images when stack protection is enabled. Notice that stack protection is not enabled by default in qemu. Fixes ARM-software/tf-issues#568 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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- 04 Mar, 2018 1 commit
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Michalis Pappas authored
The register address range of UART1 (crash console) are outside the address ranges mapped for MMIO, resulting to an MMU abort when the device registers are accessed. Increase the size of DEVICE1 memory to include the range of UART1. Fixes ARM-software/tf-issues#560 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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- 28 Feb, 2018 1 commit
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Michalis Pappas authored
Update qemu_configure_mmu_##_el to add an additional region for code, marked as MT_CODE | MT_SECURE. Update ro region attributes to NON_EXEC. Update calls to QEMU_CONFIGURE_BLx_MMU() to pass an additional region for code. Update calls to pass regions defined in common_def.h. Increase MAX_MMAP_REGIONS to 10. Enable SEPARATE_CODE_AND_RODATA by default on QEMU builds. Fixes ARM-software/tf-issues#558 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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- 27 Feb, 2018 1 commit
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David Cunado authored
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 05 Feb, 2018 1 commit
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Etienne Carriere authored
Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 26 Oct, 2017 1 commit
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Etienne Carriere authored
OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE secure RAM. To support this configuration the trusted firmware should not load OP-TEE resources in this area. To overcome the issue, OP-TEE pageable image is now loaded 2MByte above the secure RAM base address. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 24 Oct, 2017 1 commit
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Etienne Carriere authored
Before this change, plat_secondary_cold_boot_setup reads wake up mailbox as a byte array but through 64bit accesses on unaligned 64bit addresses. In the other hand qemu_pwr_domain_on wakes secondary cores by writing into a 64bit array. This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE explicitly specifies it. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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- 24 Aug, 2017 2 commits
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Jens Wiklander authored
OP-TEE may have extra images to be loaded. Load them one by one and do the parsing. In this patch, ARM TF need to load up to 3 images for OP-TEE: header, pager and pages images. Header image is the info about optee os and images. Pager image include pager code and data. Paged image include the paging parts using virtual memory. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Jens Wiklander authored
Replaces the deprecated ADDR_SPACE_SIZE with PLAT_PHY_ADDR_SPACE_SIZE and PLAT_VIRT_ADDR_SPACE_SIZE. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 18 Jan, 2017 1 commit
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Masahiro Yamada authored
I do not see any line that references BL32_SIZE. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 09 Jun, 2016 1 commit
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Jens Wiklander authored
This patch adds support for the QEMU virt ARMv8-A target. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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