- 28 Sep, 2016 1 commit
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Soby Mathew authored
This patch adds the PSCI library integration guide for AArch32 ARMv8-A systems `psci-lib-integration-guide.md` to the documentation. The patch also adds appropriate reference to the new document in the `firmware-design.md` document. Change-Id: I2d5b5c6b612452371713399702e318e3c73a8ee0
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- 27 Sep, 2016 2 commits
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davidcunado-arm authored
Upgrade Linaro release, FVPs and mbed TLS versions
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Sandrine Bailleux authored
This patch updates the User Guide to recommend the latest version of some of the software dependencies of ARM Trusted Firmware. - Upgrade Linaro release: 16.02 -> 16.06 - Upgrade FVPs - Foundation v8 FVP: 9.5 -> 10.1 - Base FVPs: 7.6 -> 7.7 - Upgrade mbed TLS library: 2.2.0 -> 2.2.1 Note that the latest release of mbed TLS as of today is 2.3.0 but it has compilations issues with the set of library configuration options that Trusted Firmware uses. 2.2.1 is the next most recent release known to build with TF. This patch also fixes the markdown formatting of a link in the User Guide. Change-Id: Ieb7dd336f4d3110fba060afec4ad580ae707a8f1
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- 26 Sep, 2016 1 commit
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davidcunado-arm authored
Whitelist version 9.6 of Foundation FVP
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- 23 Sep, 2016 3 commits
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davidcunado-arm authored
AArch32: Fix detection of virtualization support
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Yatharth Kochar authored
The Virtualization field in the ID_PFR1 register has only 2 valid values (0 or 1) but it was incorrectly checked against unrelated value tied to the SPSR register instead. This patch fixes the detection of virtualization support by using the valid values in BL1 context management code. Change-Id: If12592e343770e1da90f0f5fecf0a3376047ac29
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Sandrine Bailleux authored
This prevents a warning being emitted in the console during FVP configuration setup when using the Foundation FVP 9.6 onwards. Change-Id: I685b8bd0dbd0119af4b0cb3f7d708fcc08e99561
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- 22 Sep, 2016 4 commits
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danh-arm authored
Introduce PSCI Library argument structure
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Soby Mathew authored
This patch moves the invocation of `psci_setup()` from BL31 and SP_MIN into `std_svc_setup()` as part of ARM Standard Service initialization. This allows us to consolidate ARM Standard Service initializations which will be added to in the future. A new function `get_arm_std_svc_args()` is introduced to get arguments corresponding to each standard service. This function must be implemented by the EL3 Runtime Firmware and both SP_MIN and BL31 implement it. Change-Id: I38e1b644f797fa4089b20574bd4a10f0419de184
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Soby Mathew authored
This patch introduces a `psci_lib_args_t` structure which must be passed into `psci_setup()` which is then used to initialize the PSCI library. The `psci_lib_args_t` is a versioned structure so as to enable compatibility checks during library initialization. Both BL31 and SP_MIN are modified to use the new structure. SP_MIN is also modified to add version string and build message as part of its cold boot log just like the other BLs in Trusted Firmware. NOTE: Please be aware that this patch modifies the prototype of `psci_setup()`, which breaks compatibility with EL3 Runtime Firmware (excluding BL31 and SP_MIN) integrated with the PSCI Library. Change-Id: Ic3761db0b790760a7ad664d8a437c72ea5edbcd6
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danh-arm authored
Add basic AArch32 support for BL1 & BL2
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- 21 Sep, 2016 9 commits
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Yatharth Kochar authored
This patch adds ARM Cortex-A32 MPCore Processor support in the CPU specific operations framework. It also includes this support for the Base FVP port. Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d
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Yatharth Kochar authored
This patch adds support in SP_MIN to receive generic and platform specific arguments from BL2. The new signature is as following: void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2); ARM platforms have been modified to use this support. Note: Platforms may break if using old signature. Default value for RESET_TO_SP_MIN is changed to 0. Change-Id: I008d4b09fd3803c7b6231587ebf02a047bdba8d0
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Yatharth Kochar authored
This patch uses the `el3_entrypoint_common` macro to initialize CPU registers, in SP_MIN entrypoint.s file, in both cold and warm boot path. It also adds conditional compilation, in cold and warm boot entry path, based on RESET_TO_SP_MIN. Change-Id: Id493ca840dc7b9e26948dc78ee928e9fdb76b9e4
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Yatharth Kochar authored
This patch adds ARM platform changes in BL2 for AArch32 state. It instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL32` and `BL33`. It also enables building of BL2 for ARCH=aarch32. Change-Id: I60dc7a284311eceba401fc789311c50ac746c51e
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Yatharth Kochar authored
This patch adds generic changes in BL2 to support AArch32 state. New AArch32 specific assembly/C files are introduced and some files are moved to AArch32/64 specific folders. BL2 for AArch64 is refactored but functionally identical. BL2 executes in Secure SVC mode in AArch32 state. Change-Id: Ifaacbc2a91f8640876385b953adb24744d9dbde3
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Yatharth Kochar authored
This patch adds ARM platform changes in BL1 for AArch32 state. It also enables building of BL1 for ARCH=aarch32. Change-Id: I079be81a93d027f37b0f7d8bb474b1252bb4cf48
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Yatharth Kochar authored
This patch adds generic changes in BL1 to support AArch32 state. New AArch32 specific assembly/C files are introduced and some files are moved to AArch32/64 specific folders. BL1 for AArch64 is refactored but functionally identical. BL1 executes in Secure Monitor mode in AArch32 state. NOTE: BL1 in AArch32 state ONLY handles BL1_RUN_IMAGE SMC. Change-Id: I6e2296374c7efbf3cf2aa1a0ce8de0732d8c98a5
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Yatharth Kochar authored
This patch adds common changes to support AArch32 state in BL1 and BL2. Following are the changes: * Added functions for disabling MMU from Secure state. * Added AArch32 specific SMC function. * Added semihosting support. * Added reporting of unhandled exceptions. * Added uniprocessor stack support. * Added `el3_entrypoint_common` macro that can be shared by BL1 and BL32 (SP_MIN) BL stages. The `el3_entrypoint_common` is similar to the AArch64 counterpart with the main difference in the assembly instructions and the registers that are relevant to AArch32 execution state. * Enabled `LOAD_IMAGE_V2` flag in Makefile for `ARCH=aarch32` and added check to make sure that platform has not overridden to disable it. Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
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Yatharth Kochar authored
This patch adds changes in ARM platform code to use new version of image loading. Following are the major changes: -Refactor the signatures for bl31_early_platform_setup() and arm_bl31_early_platform_setup() function to use `void *` instead of `bl31_params_t *`. -Introduce `plat_arm_bl2_handle_scp_bl2()` to handle loading of SCP_BL2 image from BL2. -Remove usage of reserve_mem() function from `arm_bl1_early_platform_setup()` -Extract BL32 & BL33 entrypoint info, from the link list passed by BL2, in `arm_bl31_early_platform_setup()` -Provides weak definitions for following platform functions: plat_get_bl_image_load_info plat_get_next_bl_params plat_flush_next_bl_params bl2_plat_handle_post_image_load -Instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL31`, `BL32` and `BL33` images. All the above changes are conditionally compiled using the `LOAD_IMAGE_V2` flag. Change-Id: I5e88b9785a3df1a2b2bbbb37d85b8e353ca61049
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- 20 Sep, 2016 2 commits
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Yatharth Kochar authored
This patch adds changes in BL1 & BL2 to use new version of image loading to load the BL images. Following are the changes in BL1: -Use new version of load_auth_image() to load BL2 -Modified `bl1_init_bl2_mem_layout()` to remove using `reserve_mem()` and to calculate `bl2_mem_layout`. `bl2_mem_layout` calculation now assumes that BL1 RW data is at the top of the bl1_mem_layout, which is more restrictive than the previous BL1 behaviour. Following are the changes in BL2: -The `bl2_main.c` is refactored and all the functions for loading BLxx images are now moved to `bl2_image_load.c` `bl2_main.c` now calls a top level `bl2_load_images()` to load all the images that are applicable in BL2. -Added new file `bl2_image_load_v2.c` that uses new version of image loading to load the BL images in BL2. All the above changes are conditionally compiled using the `LOAD_IMAGE_V2` flag. Change-Id: Ic6dcde5a484495bdc05526d9121c59fa50c1bf23
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Yatharth Kochar authored
This patch adds capability to load BL images based on image descriptors instead of hard coded way of loading BL images. This framework is designed such that it can be readily adapted by any BL stage that needs to load images. In order to provide the above capability the following new platform functions are introduced: bl_load_info_t *plat_get_bl_image_load_info(void); This function returns pointer to the list of images that the platform has populated to load. bl_params_t *plat_get_next_bl_params(void); This function returns a pointer to the shared memory that the platform has kept aside to pass trusted firmware related information that next BL image needs. void plat_flush_next_bl_params(void); This function flushes to main memory all the params that are passed to next image. int bl2_plat_handle_post_image_load(unsigned int image_id) This function can be used by the platforms to update/use image information for given `image_id`. `desc_image_load.c` contains utility functions which can be used by the platforms to generate, load and executable, image list based on the registered image descriptors. This patch also adds new version of `load_image/load_auth_image` functions in-order to achieve the above capability. Following are the changes for the new version as compared to old: - Refactor the signature and only keep image_id and image_info_t arguments. Removed image_base argument as it is already passed through image_info_t. Given that the BL image base addresses and limit/size are already provided by the platforms, the meminfo_t and entry_point_info arguments are not needed to provide/reserve the extent of free memory for the given BL image. - Added check for the image size against the defined max size. This is needed because the image size could come from an unauthenticated source (e.g. the FIP header). To make this check, new member is added to the image_info_t struct for identifying the image maximum size. New flag `LOAD_IMAGE_V2` is added in the Makefile. Default value is 0. NOTE: `TRUSTED_BOARD_BOOT` is currently not supported when `LOAD_IMAGE_V2` is enabled. Change-Id: Ia7b643f4817a170d5a2fbf479b9bc12e63112e79
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- 19 Sep, 2016 8 commits
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danh-arm authored
Remove MT6795 plat_sip_svc.c to fix Coverity analysis error.
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danh-arm authored
fiptool: Invoke command specific usage function
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danh-arm authored
Ensure PMF service timestamps are properly aligned on a cache line bo…
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danh-arm authored
Rename `pmf_calc_timestamp_offset` to `pmf_calc_timestamp_addr`
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danh-arm authored
GICv3: Allow either G1S or G0 interrupts to be configured
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danh-arm authored
Support for PSCI NODE_HW_STATE
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danh-arm authored
fiptool: Add support for printing the sha256 digest with info command
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Leon Chen authored
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- 16 Sep, 2016 1 commit
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davidcunado-arm authored
xilinx: ZynqMP updates - new SIP calls for bitstream programming - new SIP call to discover the SOC silicon version - support the delay timer
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- 15 Sep, 2016 9 commits
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Jeenu Viswambharan authored
This patch implements CSS platform hook to support NODE_HW_STATE PSCI API. The platform hook queries SCP to obtain CSS power state. Power states returned by SCP are then converted to expected PSCI return codes. Juno's PSCI operation structure is modified to use the CSS implementation. Change-Id: I4a5edac0e5895dd77b51398cbd78f934831dafc0
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Jeenu Viswambharan authored
This patch adds the function scpi_get_css_power_state to perform the 'Get CSS Power State' SCP command and handle its response. The function parses SCP response to obtain power states of requested cluster and CPUs within. Change-Id: I3ea26e48dff1a139da73f6c1e0893f21accaf9f0
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Jeenu Viswambharan authored
This patch implements FVP platform hook to support NODE_HW_STATE PSCI API. The platform hook validates the given MPIDR and reads corresponding status from FVP power controller, and returns expected values for the PSCI call. Change-Id: I286c92637da11858db2c8aba8ba079389032de6d
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Jeenu Viswambharan authored
This patch adds support for NODE_HW_STATE PSCI API by introducing a new PSCI platform hook (get_node_hw_state). The implementation validates supplied arguments, and then invokes this platform-defined hook and returns its result to the caller. PSCI capabilities are updated accordingly. Also updates porting and firmware design guides. Change-Id: I808e55bdf0c157002a7c104b875779fe50a68a30
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davidcunado-arm authored
Restore some defines in xlat_tables.h
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davidcunado-arm authored
Add some missing forward declarations in plat_arm.h
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Sandrine Bailleux authored
This patch adds a couple of missing forward declarations in plat_arm.h so that all types it references are known within this header file, without relying on previous header inclusions. This concerns the meminfo and bl31_params structures, which are defined in bl_common.h. Other external types referenced from plat_arm.h (e.g. mmap_region_t) get declared through header files included by arm_plat.h so they don't need forward declarations. Change-Id: I471d5aa487919aff3fa979fc65e053f4f5b0ef32
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Sandrine Bailleux authored
Commit e8719552 removed some definitions related to translation tables from the xlat_tables.h header file, based on the assumption that they weren't used by any platform. These are actually used by some partners so this patch restores them. Fixes ARM-software/tf-issues#425 Change-Id: Idafa5f00bb0bd9c2847b5ae6541cf8db93c7b89a
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dp-arm authored
Instead of always calling the top level usage function when an error is detected, call the command-specific usage function. For example running `fiptool create` will produce the same output as `fiptool help create`. This is more convenient for the user when they make a mistake. Change-Id: I60178ab89d47adf93cdfe6d8b5d5f778a5ea3bca
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