- 26 Jul, 2021 1 commit
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Manish Pandey authored
* changes: fix(plat/tc0): enable AMU extension fix(el3_runtime): fix SVE and AMU extension enablement flags
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- 25 Jul, 2021 1 commit
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Joanna Farley authored
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- 24 Jul, 2021 2 commits
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Joanna Farley authored
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Peng Fan authored
Add myself as i.MX8 maintainer. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58
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- 23 Jul, 2021 3 commits
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Madhukar Pappireddy authored
* changes: feat: disabling non volatile counters in diphda feat: adding the diphda platform
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Arunachalam Ganapathy authored
Recent changes to enable SVE for the secure world have disabled AMU extension by default in the reset value of CPTR_EL3 register. So the platform has to enable this extension explicitly. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I7d930d96ec22d7c3db961411370564bece0ce272
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Arunachalam Ganapathy authored
If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087
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- 22 Jul, 2021 6 commits
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Abdellatif El Khlifi authored
At this stage of development Non Volatile counters are not implemented in the Diphda platform. This commit disables their use during the Trusted Board Boot by overriding the NV counters get/set functions. Change-Id: I8dcbebe0281cc4d0837c283ff637e20b850988ef Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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Abdellatif El Khlifi authored
This commit enables trusted-firmware-a with Trusted Board Boot support for the Diphda 64-bit platform. Diphda uses a FIP image located in the flash. The FIP contains the following components: - BL2 - BL31 - BL32 - BL32 SPMC manifest - BL33 - The TBB certificates The board boot relies on CoT (chain of trust). The trusted-firmware-a BL2 is extracted from the FIP and verified by the Secure Enclave processor. BL2 verification relies on the signature area at the beginning of the BL2 image. This area is needed by the SecureEnclave bootloader. Then, the application processor is released from reset and starts by executing BL2. BL2 performs the actions described in the trusted-firmware-a TBB design document. Signed-off-by: Rui Miguel Silva <rui.silva@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
* changes: fix(drivers/scmi-msg): entry: add weak functions feat(drivers/scmi-msg): add power domain protocol fix(drivers/scmi-msg): smt: fix build for aarch64
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Peng Fan authored
One platform may not implement all the protocols, to avoid build break when we not include all the protocols, add weak functions. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I1485baa2e8f381cb0eede1a7b93ed10e49934971
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Peng Fan authored
Add SCMI power domain protocol, with POWER_STATE_NOTIFY and POWER_STATE_CHANGE_REQUESTED_NOTIFY not implemented. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: Ia7c4db57c4c702667f8eaa630c924016e4a8bde0
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- 21 Jul, 2021 1 commit
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Roger Lu authored
Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I6dbf6d4ea6310c3371ca15d1e7cce249a05af2fb
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- 20 Jul, 2021 4 commits
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Madhukar Pappireddy authored
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Manish Pandey authored
* changes: refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers refactor(plat/arm): mark the flash region as read-only refactor(plat/arm): update NV flags on image load/authentication failure
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Manish Pandey authored
* changes: fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable fix(plat/marvell/a3k): Fix check for external dependences fix(plat/marvell/a8k): Add missing build dependency for BLE target fix(plat/marvell/a8k): Correctly set include directories for individual targets fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set
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Garmin Chang authored
There is a error setting for SPM, so we need to fix this issue. Signed-off-by: Garmin Chang <garmin.chang@mediatek.com> Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57
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- 19 Jul, 2021 7 commits
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bipin.ravi authored
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johpow01 authored
Neoverse V1 erratum 1940577 is a Cat B erratum, present in some revisions of the V1 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r1p1 but this workaround only applies to revisions r1p0 - r1p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa
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Madhukar Pappireddy authored
* changes: refactor(plat/nxp/lx216x): refine variable definition refactor(plat/nxp/lx216x): use common make variables
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Madhukar Pappireddy authored
* changes: docs: add mt6795 to deprecated list feat(plat/mediatek/mt8195): add DCM driver
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bipin.ravi authored
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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- 17 Jul, 2021 1 commit
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Rex-BC Chen authored
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2b3aa9bd0c23c360ecee673c68e1b2c92bc6d2be
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- 16 Jul, 2021 3 commits
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johpow01 authored
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
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Pali Rohár authored
INFO() macro for every call prepends "INFO: " string. Therefore current code prints unreadable debug messages: "INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0)INFO: " "INFO: Set IO decode window successfully, base(0xc000)INFO: win_attr(3d) max_dram_win(2) max_remap(0)INFO: win_offset(8)" Fix it by calling exactly one INFO() call for one line. After this change output is: "INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0) remap(0x0)" "INFO: Set IO decode window successfully, base(0xc000) win_attr(3d) max_dram_win(2) max_remap(0) win_offset(8)" Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I6084e64c6f4da6c1929e5300588e4ba2608ca745
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Madhukar Pappireddy authored
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- 15 Jul, 2021 1 commit
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Peng Fan authored
For AARCH64, BIT() will make the number as ULL type, let use BIT_32() here. And use %zu for size_t print format. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I1dc18d374cd2c6eb83b40b66ed6189dcc6a21728
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- 13 Jul, 2021 2 commits
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Madhukar Pappireddy authored
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Joanna Farley authored
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- 12 Jul, 2021 3 commits
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Manish V Badarkhe authored
Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Julius Werner authored
The two existing plat/rockchip code owners seem to be no longer active in the project and are not responding to reviews. There have been a couple of small fixup patches[1][2][3] pending for months that couldn't be checked in for lack of Code-Owner-Review+1 flag. Add myself to the code owner list to unblock this bottleneck (I have been deeply involved in the rk3399 port, at least, so I know most of the code reasonably well). [1] https://review.trustedfirmware.org/9616 [2] https://review.trustedfirmware.org/9990 [2] https://review.trustedfirmware.org/10415 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic7b2bb73c35a9bea91ff46ee445a22819d2045d9
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Manish Pandey authored
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- 11 Jul, 2021 2 commits
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Pali Rohár authored
For UART secure boot it is required also TIMN image, so pack it into uart-images.tgz.bin archive which is created by mrvl_uart target. $(TIMN_IMAGE) and $(TIM_IMAGE) variables are used only for UART images so their content needs to be initialized from $(TIMN_UART_CFG) and $(TIM_UART_CFG) config files. And not from $(TIMN_CFG) and $(TIM_CFG) as it is now because they are not generated during mrvl_uart target. Fix it to allow building mrvl_uart target before mrvl_flash target. To match usage of these variables, rename them to $(TIMN_UART_IMAGE) and $(TIM_UART_IMAGE). To not complicate rule for building uart-images.tgz.bin archive, set list of image files into a new $(UART_IMAGES) variable. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I83b980abb4047a3afb3ce3026842e1d873c490bf
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Pali Rohár authored
For TIM config file use TIM name instead of DOIMAGE and use underscores to make variable names more readable. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I1282ce11f1431c15458a143ae7bfcee85eed2432
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- 10 Jul, 2021 3 commits
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Pali Rohár authored
Armada 3700 uses external TBB tool for creating images and does not use internal TF-A doimage tool from tools/marvell/doimage/ Therefore set correct name of variable. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I38a94dca78d483de4c79da597c032e1e5d06d92d
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Pali Rohár authored
Armada 3700 uses WTP so use WTP variable directly. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I216b40ffee1f3f8abba4677f050ab376c2224ede
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Pali Rohár authored
Old Marvell a3700_utils and mv-ddr tarballs do not have to work with latest TF-A code base. Marvell do not provide these old tarballs on Extranet anymore. Public version on github repository contains all patches and is working fine, so for public TF-A builds use only public external dependencies from git. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61
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