- 04 Jan, 2019 2 commits
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Even though this is not used unless SPD=tspd, only defining it when SPD_tspd is defined doesn't have any advantage and it makes it harder to read the code. Change-Id: I3d93135e05f39be071d16f8a47394a9a3ff54bc8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 19 Dec, 2018 1 commit
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Antonio Nino Diaz authored
This option was removed in v2.0. Change-Id: I0c929fddb57d60c5eff9e45dd5ee8c636b28e6c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 1 commit
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Sathees Balya authored
This patch allows platforms to define their own jump table list for library at ROM. The file has the list of functions to be used from library at ROM. It can also include other list files. Change-Id: I721c35d7dad3dcadbb3a7f3277bfd5d3e1f6e00a Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 11 Dec, 2018 3 commits
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Antonio Nino Diaz authored
Change-Id: Ib7c2529b85bb5930d44907edfc8ead13d3b1ef4d Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
SPM needs to map a number of regions on behalf of the secure partition. Previously, it used to get a list of them from platform code using the plat_get_secure_partition_mmap() API. Now it gets them from the resource description structure. The SPM<->SP shared buffer is mapped dynamically at EL3. This buffer is used to pass information between SPM and SP, so it must be mapped at EL3 as well in order to be used by SPM. Dynamic translation tables have been enabled when the Trusted Firmware is compiled with SPM support. Change-Id: I64ad335e931661812a0a60558e60372e1e5e6b72 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Load SP and RD from package instead of relying on RD being already loaded in memory and the SP being loaded as a BL32 image. Change-Id: I18d4fbf4597656c6a7e878e1d7c01a8a324f3f8a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Dec, 2018 4 commits
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Antonio Nino Diaz authored
This information is retrieved from the resource description now. Change-Id: Iaae23945eb2c45305cdc6442853e42f4e04fe094 Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This information is defined by the Secure Partition in the resource description. Change-Id: Ia7db90c5de8360a596106880d3f6a632a88d3ea8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Introduce helpers to create resource description struct, as well as code to load the information from DTB files. Change-Id: I0f5bb94eb8b01c6cb53fe807a9db0c05a70d7a43 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Iec265dc85d44f35048d1fbcfbe55960d45570027 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Dec, 2018 3 commits
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Chandni Cherukuri authored
SGI-Clark.Helios platform is similar to SGI-Clark.Ares platform. The difference between these two platforms is the CPU type and the number of CPUs. Add the base support for SGI-Clark.Helios platform. Change-Id: I2b04cb3fb953907848b4fab016e3648899ca4256 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
For SGI-Clark.Helios platform, at present, only the CPU power ON/OFF ops are supported. So override the PSCI ops to allow callbacks only for CPU power ON/OFF operations. Change-Id: Idc0a3deb78cb850310cbe849d77604fa9881579c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
SGI-Clark.Helios platform is based on multi-threaded CPUs and uses an additional thread power domain level as well. Define a power domain tree descriptor 'sgi_clark_helios_pd_tree_desc' for SGI-Clark.Helios platform and let the function 'plat_get_power_domain_tree_desc' pick up the correct power domain tree descriptor based on the platform. Change-Id: Ibc6d551b570bc740053316a3608c455679d9155b Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 05 Dec, 2018 1 commit
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Chandni Cherukuri authored
With the two new APIs 'plat_arm_sgi_get_platform_id' and 'plat_arm_sgi_get_config_id' that are available now, BL31 need not depend on hw_config device tree to identify the platform. In addition to this, the existing hardware description in hw_config can be limited to use by BL33 and not by the operating system. So the hardware description from hw_config dts can be moved into nt_fw_config dts and the use of hw_config dts can be removed. Change-Id: I873b7e1e72823d3ec5d253a848e85ae724f09e49 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 03 Dec, 2018 1 commit
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Chandni Cherukuri authored
Add two new functions 'plat_arm_sgi_get_platform_id' and 'plat_arm_sgi_get_config_id' which will be implemented by all the SGI platforms. These functions can be used to determine the part number and configuration id of the SGI platforms. In BL2, these functions are used to populate the 'system-id' node. In BL31, these functions are used to populate the 'sgi_plat_info_t' structure with the part number and configuration id of the platform. Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 29 Nov, 2018 1 commit
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Chandni Cherukuri authored
In order to allow Arm platforms to override the default list of PSCI callbacks, remove the existing weak implementation of 'plat_arm_psci_override_pm_ops' function and let all the Arm platforms implement their own 'plat_arm_psci_override_pm_ops' function. For platforms that support SCMI protocol, the function 'css_scmi_override_pm_ops' can be additionally used as well to override the default PSCI callbacks. Change-Id: If7c27468bd51a00ea9c2a3716b5894163f5a9f3c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 27 Nov, 2018 3 commits
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Chandni Cherukuri authored
For platforms with multi-threaded CPUs, the number of power domains supported would be more than the value currently defined by PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform specific code and let the platform define the number of power domain levels. Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
To support platforms which are based on multi-threaded CPUs, override the weak implementation of plat_arm_get_cpu_pe_count function to return the number of threads supported by the CPU used in the platform. Change-Id: Ia680773f1277b17e2d3d2414d87943dcece33e89 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 26 Nov, 2018 1 commit
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Antonio Nino Diaz authored
The headers forked at some point in the past and have diverged a lot. In order to make it easier to share code between TF-A-Tests and TF-A, this patch synchronises most of the definitions in the mentioned headers. This is not a complete sync, it has to be followed by more cleanup. This patch also removes the read helpers for the AArch32 instructions ats1cpr and ats1hr (they are write-only). Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 23 Nov, 2018 1 commit
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Sathees Balya authored
This patch adds support to build a combined BL1 and ROMLIB binary file with the right page alignment in Juno. When USE_ROMLIB=1 is set for Juno, it generates the combined file bl1_romlib.bin which needs to be used instead of bl1.bin Change-Id: I407efbe48d3e522fa6ef855538a9587193cb1919 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
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- 21 Nov, 2018 1 commit
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Vijayenthiran Subramaniam authored
Remove the platform common plat_arm_security_setup function to allow platform specific implementations of the security setup function implemented in the board directory of the platform. For use by secure software, configure region0 of DMC-620 trustzone controller to protect the upper 16MB of memory of the first DRAM block from non-secure accesses. Change-Id: I9a8c19656702c4fa4f6917b3655b692d443bb568 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 14 Nov, 2018 1 commit
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Sughosh Ganu authored
Register a priority level, PLAT_SP_PRI, for secure partition with EL3 exception handling framework(ehf) module. The secure partition manager(SPM) would raise the core's priority to PLAT_SP_PRI before entering the secure partition, to protect the core from getting interrupted while in secure partition. Change-Id: I686897f052a4371e0efa9b929c07d3ad77249e95 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Nov, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 05 Nov, 2018 1 commit
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Manish Pandey authored
This option allows the Trusted Firmware to directly jump to Linux kernel for aarch32 without the need of an intermediate loader such as U-Boot. Similar to AArch64 ARM_LINUX_KERNEL_AS_BL33 only available with RESET_TO_SP_MIN=1 as well as BL33 and DTB are preloaded in memory. Change-Id: I908bc1633696be1caad0ce2f099c34215c8e0633 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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- 01 Nov, 2018 4 commits
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Sudeep Holla authored
When CSS_USE_SCMI_DRIVER is not defined or set to 0, we get the following build error. plat/arm/board/juno/juno_topology.c:16:19: error: ‘CSS_SCMI_PAYLOAD_BASE’ undeclared here (not in a function) .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, ^~~~~~~~~~~~~~~~~~~~~ plat/arm/board/juno/juno_topology.c:17:38: error: ‘CSS_SCMI_MHU_DB_REG_OFF’ undeclared here (not in a function) .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, ^~~~~~~~~~~~~~~~~~~~~~~ CSS_CPU_PWR_STATE_OFF Fix the error in order to get function legacy SCPI support functional. Change-Id: I00cb80db9968aa0be546e33a3a682a2db87719be Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Antonio Nino Diaz authored
Change-Id: Iae6758ca6395560131d1e1a69a1ecfe50ca8bf83 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 29 Oct, 2018 5 commits
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Antonio Nino Diaz authored
No functional changes. Change-Id: I9b9f8d3dfde08d57706ad5450de6ff858a55ac01 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Deepak Pandey authored
This patch adds support for the N1SDP (NeoVerse N1 System Development Platform). It is an initial port and additional features are expected to be added later. The port includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary boatloader Change-Id: Ife17d8215a7bfcc1420204a72205e7ef920d0c10 Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
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Soby Mathew authored
This patch enabled PIE for FVP when RESET_TO_BL31=1. The references to BL31_BASE are replaced by BL31_START as being a symbol exported by the linker, will create a dynamic relocation entry in .rela.dyn and hence will be fixed up by dynamic linker at runtime. Also, we disable RECLAIM_INIT_CODE when PIE is enabled as the init section overlay creates some static relocations which cannot be handled by the dynamic linker currently. Change-Id: I86df1b0a8b2a8bbbe7c3f3c0b9a08c86c2963ec0 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch makes use of mov_imm macro where possible to load immediate values within ARM platform layer. Change-Id: I02bc7fbc1fa334c9fccf76fbddf515952f9a1298 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Soby Mathew authored
This patch adds a utility function to return the address of a symbol. By default, the compiler generates adr/adrp instruction pair to return the reference and this utility is used to override this compiler generated to code and use `ldr` instruction. This is needed for Position Independent Executable when it needs to reference a symbol which is constant and does not depend on the execute address of the binary. For example, on the FVP, the GICv3 register context is stored in a secure carveout (arm_el3_tzc_dram) within DDR and does not relocate with the BL image. Now if BL31 is executing at a different address other than the compiled address, using adrp/adr instructions to reference this memory will not work as they generate an address that is PC relative. The way to get around this problem is to reference it as non-PC relative (i.e non-relocatable location) via `ldr` instruction. Change-Id: I5008a951b007144258121690afb68dc8e12ee6f7 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 26 Oct, 2018 4 commits
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Roberto Vargas authored
This function is not related to Arm platforms and can be reused by other platforms if needed. Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
There are several platforms using arm_setup_page_tables(), which is supposed to be Arm platform only. This creates several dependency problems between platforms. This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib v2 makefile. This way it is possible to detect from C code which version is being used and include the correct header. The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and moved to a common folder. This way, when in doubt, this header can be used to guarantee compatibility, as it includes the correct header based on XLAT_TABLES_LIB_V2. This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so that is now locked in xlat lib v2) and ZynqMP (where it was added as a workaround). Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Chandni Cherukuri authored
SGI-Clark.Ares platform is a variant of the SGI-Clark platform. It has two clusters of four Ares CPUs each. Though very similar to the SGI575 platform, there are subtle differences. HW_CONFIG and TB_FW_CONFIG dts files have been added. Change-Id: I740a33cbd1c3b1f1984cb56243b46ad379bab3e6 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
SGI-Clark platform is the next version in the Arm's SGI platform series. One of the primary difference between the SGI-575 platform and the SGI-Clark platform is the MHU version (MHUv2 in case of SGI-Clark). Add the required base support for SGI-Clark platform. Change-Id: If396e5279fdf801d586662dad0b55195e81371e4 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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