Skip to content

GitLab

Switch branch/tag
  1. 25 Sep, 2020 1 commit
  3. 10 Sep, 2020 1 commit
  5. 02 Sep, 2020 1 commit
    • Pramod Kumar's avatar
      lib: cpu: Check SCU presence in DSU before accessing DSU registers · 942013e1
      Pramod Kumar authored 
      

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3
memory system variant is used, there won't be any L3 cache,
snoop filter, and SCU logic present hence no system control register
will be present. Hence check SCU presence before accessing DSU register
for DSU_936184 errata.
Signed-off-by: default avatarPramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63
      942013e1
  7. 31 Aug, 2020 3 commits
  9. 24 Aug, 2020 1 commit
    • Varun Wadekar's avatar
      lib: cpus: sanity check pointers before use · 601e3ed2
      Varun Wadekar authored 
      

The cpu_ops structure contains a lot of function pointers. It
is a good idea to verify that the function pointer is not NULL
before executing it.

This patch sanity checks each pointer before use to prevent any
unforeseen crashes. These checks have been enabled for debug
builds only.

Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      601e3ed2
  11. 18 Aug, 2020 1 commit
    • Manish V Badarkhe's avatar
      lib/cpus: Report AT speculative erratum workaround · e1c49333
      Manish V Badarkhe authored 
      

Reported the status (applies, missing) of AT speculative workaround
which is applicable for below CPUs.

 +---------+--------------+
 | Errata  |      CPU     |
 +=========+==============+
 | 1165522 |  Cortex-A76  |
 +---------+--------------+
 | 1319367 |  Cortex-A72  |
 +---------+--------------+
 | 1319537 |  Cortex-A57  |
 +---------+--------------+
 | 1530923 |  Cortex-A55  |
 +---------+--------------+
 | 1530924 |  Cortex-A53  |
 +---------+--------------+

Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT'
if AT speculative errata workaround is enabled for any of the above
CPUs using 'ERRATA_*' CPU specific build macro.
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b
      e1c49333
  13. 09 Aug, 2020 2 commits
  15. 23 Jul, 2020 1 commit
  17. 25 Jun, 2020 2 commits
  19. 22 Jun, 2020 2 commits
  21. 09 Jun, 2020 1 commit
    • Varun Wadekar's avatar
      cpus: denver: disable cycle counter when event counting is prohibited · c5c1af0d
      Varun Wadekar authored 
      

The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the
PMCR_EL0 to be saved in non-secure context.

This patch disables cycle counter when event counting is prohibited
immediately on entering the secure world to avoid leaking useful
information about the PMU counters. The context saving code later
saves the value of PMCR_EL0 to the non-secure world context.

Verified with 'PMU Leakage' test suite.

 ******************************* Summary *******************************
 > Test suite 'PMU Leakage'
                                                                 Passed
 =================================
 Tests Skipped : 2
 Tests Passed  : 2
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 4
 =================================
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875
      c5c1af0d
  23. 01 Jun, 2020 2 commits
  25. 09 Mar, 2020 1 commit
  27. 20 Feb, 2020 1 commit
    • Varun Wadekar's avatar
      cpus: higher performance non-cacheable load forwarding · cd0ea184
      Varun Wadekar authored 
      

The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
non-cacheable streaming enhancement. Platforms can set this bit only
if their memory system meets the requirement that cache line fill
requests from the Cortex-A57 processor are atomic.

This patch adds support to enable higher performance non-cacheable load
forwarding for such platforms. Platforms must enable this support by
setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
makefiles. This flag is disabled by default.

Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      cd0ea184
  29. 18 Feb, 2020 2 commits
  31. 04 Feb, 2020 1 commit
  33. 27 Jan, 2020 1 commit
  35. 23 Jan, 2020 1 commit
  37. 22 Jan, 2020 1 commit
  39. 23 Dec, 2019 1 commit
  41. 24 Oct, 2019 1 commit
  43. 04 Oct, 2019 1 commit
    • laurenw-arm's avatar
      Neoverse N1 Errata Workaround 1542419 · 80942622
      laurenw-arm authored 
      

Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.

The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.
Signed-off-by: default avatarLauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
      80942622
  45. 03 Oct, 2019 1 commit
  47. 02 Oct, 2019 1 commit
  49. 30 Sep, 2019 1 commit
  51. 11 Sep, 2019 1 commit
  53. 19 Aug, 2019 1 commit
  55. 16 Aug, 2019 1 commit
    • Alexei Fedorov's avatar
      FVP_Base_AEMv8A platform: Fix cache maintenance operations · ef430ff4
      Alexei Fedorov authored 
      

This patch fixes FVP_Base_AEMv8A model hang issue with
ARMv8.4+ with cache modelling enabled configuration.
Incorrect L1 cache flush operation to PoU, using CLIDR_EL1
LoUIS field, which is required by the architecture to be
zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced
with L1 to L2 and L2 to L3 (if L3 is present) cache flushes.
FVP_Base_AEMv8A model can be configured with L3 enabled by
setting `cluster0.l3cache-size` and `cluster1.l3cache-size`
to non-zero values, and presence of L3 is checked in
`aem_generic_core_pwr_dwn` function by reading
CLIDR_EL1.Ctype3 field value.

Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      ef430ff4
  57. 01 Aug, 2019 1 commit
    • Julius Werner's avatar
      Switch AARCH32/AARCH64 to __aarch64__ · 402b3cf8
      Julius Werner authored 
      

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      402b3cf8
  59. 31 Jul, 2019 1 commit
  61. 16 Jul, 2019 1 commit
  63. 10 Jul, 2019 1 commit
  65. 02 Jul, 2019 1 commit