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DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677

This fixes a few issues on the Agilex clock configuration:
- Set clock manager into boot mode before configuring clock
- Fix wrong divisor used when calculating vcocalib
- PLL sync configuration should be read and then written
- Wait PLL lock after PLL sync configuration is done
- Clear interrupt bits instead of set interrupt bits after configuration
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70

Current value is 16, count the MAP_REGION calls gets us at least 17,
so increase the max value to 20 to have a bit of a margin.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I93d0324f3d483758366e758f8f663545d365e03f

64KB was not enouth to handle fdt, bl2 shows
following error message.

"ERROR:   Invalid Device Tree at 0x10000000000: error -3"

This patch increases the size to 1MB to address above error.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I0726a0cea95087175451da0dba7410acd27df808

Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign both to secure world only.

Define stm32mp15 SoC identifiers for the platform specific DECPROT
instances.

Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

BL31_CACHE_DISABLE flag was introduced as a work-around
for the older SoC revisions. Since it is not relevant in the
newest versions, toggle it to be disabled by default.
One can still specify it by adding 'BL31_CACHE_DISABLE=1'
string to the build command.

Change-Id: I11b52dade3ff7f8ee643b8078c6e447c45946570
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
table section in spm_mm.

In the commit 363830df

 (xlat_tables_v2: merge
REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
macro explicitly specifies the base xlat table goes into .bss by default.
This change affects the existing SynQuacer spm_mm implementation.
plat/socionext/synquacer/include/plat.ld.S linker script intends to
locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
but this implementation is no longer available.

This patch adds the base table section name parameter for
REGISTER_XLAT_CONTEXT2 so that platform can specify the
inner & outer WBWA & shareable memory for spm_mm base xlat table.
If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
goes into .bss by default, the result is same as before.

Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

This should allow git to easily track file moves
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327

This allows to build for k3-based boards that use a different UART as
console, such as the IOT2050 which requires K3_USART=1.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I7171f86c3cabae2c575b8fbeecef839b48bd109b

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

The patch fixes BL31 linker script error
"Init code ends past the end of the stacks"
for platforms with number of CPUs less than 4,
which is caused by __STACKS_END__ address being
lower than __INIT_CODE_END__.
The modified BL31 linker script detects such cases
and increases the total amount of stack memory,
setting __STACKS_END__ = __INIT_CODE_END__, and
CPUs' stacks are calculated by BL31 'plat_get_my_stack'
function accordingly. For platforms with more than 4 CPUs
and __INIT_CODE_END__ < __STACKS_END__ stack memory does not
increase and allocated CPUs' stacks match the existing
implementation.
The patch removes exclusion of PSCI initialization
functions from the reclaimed .init section in
'arm_reclaim_init.ld.S' script, which increases the
size of reclaimed memory region.

Change-Id: I927773e00dd84e1ffe72f9ee534f4f2fc7b6153c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>

Fixed build error for dualroot chain of trust.
Build error were thrown as below while compiling the code for
dualroot chain of trust:

aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.bss.auth_img_flags+0x0): multiple definition of `auth_img_flags';
./build/fvp/debug/bl1/cot.o:(.bss.auth_img_flags+0x0): first defined here

aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.rodata.cot_desc_size+0x0): multiple definition of `cot_desc_size';
./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_size+0x0): first defined here

aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.rodata.cot_desc_ptr+0x0): multiple definition of `cot_desc_ptr';
./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_ptr+0x0): first defined here
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I1a426c4e7f5f8013d71dafc176c7467c1b329757

PSCI demands that SYSTEM_OFF must not return. While it seems like a
generic ATF bug that this is possible when a platform does not Implement
a corresponding handler, let's do that here until it's addressed
differently.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I4c08948b18bbfdc3a24214f2ae0fbad9e017ada1

SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA FF-A(in documents)
or simply FFA(in code).

Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760
Signed-off-by: J-Alves <joao.alves@arm.com>

Add imx8mn basic support
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d

We query the UART base address and clk frequency in runtime
using fconf getter APIs.

Change-Id: I5f4e84953be5f384472bf90720b706d45cb86260
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

This patch introduces the populate function which leverages
a new driver to extract base address and clk frequency properties
of the uart serial node from HW_CONFIG device tree.

This patch also introduces fdt helper API fdtw_translate_address()
which helps in performing address translation.

Change-Id: I053628065ebddbde0c9cb3aa93d838619f502ee3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.

* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events

Verified using TFTF SDEI test suite.

******************************* Summary *******************************
 Test suite 'SDEI'                                               Passed
 =================================
 Tests Skipped : 0
 Tests Passed  : 5
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 5
 =================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390

This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.

The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d

Query the GICD and GICR base addresses in runtime using fconf getter
APIs.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I309fb2874f3329ddeb8677ddb53ed4c02199a1e9

CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c
and tbbr_cot_bl2.c respectively.
Common CoT used across BL1 and BL2 are moved to
tbbr_cot_common.c.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5

This patch sets ENABLE_STACK_PROTECTOR=strong and implements
the platform support to generate a stack protection canary value.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ia8afe464b5645917b1c77d49305d19c7cd01866a

This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.

Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Currently BL2 passes TOS_FW_CONFIG address and size through registers to
BL31. This corresponds to SPMC manifest load address and size. The SPMC
manifest is mapped in BL31 by dynamic mapping. This patch removes BL2
changes from generic code (which were enclosed by SPD=spmd) and retrieves
SPMC manifest size directly from within SPMD. The SPMC manifest load
address is still passed through a register by generic code.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I35c5abd95c616ae25677302f0b1d0c45c51c042f

As a follow-up to bdd2596d

, and related to SPM Dispatcher
EL3 component and SPM Core S-EL2/S-EL1 component: update
with cosmetic and coding rules changes. In addition:
-Add Armv8.4-SecEL2 arch detection helper.
-Add an SPMC context (on current core) get helper.
-Return more meaningful error return codes.
-Remove complexity in few spmd_smc_handler switch-cases.
-Remove unused defines and structures from spmd_private.h
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I99e642450b0dafb19d3218a2f0e2d3107e8ca3fe

This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.

Verified using TFTF SMCCC_ARCH_SOC_ID test.

<snip>
> Executing 'SMCCC_ARCH_SOC_ID test'
  TEST COMPLETE                                                 Passed
SOC Rev = 0x102
SOC Ver = 0x36b0019
<snip>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44

New helper functions to get GPIO banks configuration from the FDT.

stm32_get_gpio_bank_pinctrl_node() allows stm32mp platforms to
differentiate specific GPIO banks when these are defined with a specific
path in the FDT.

fdt_get_gpio_bank_pin_count() returns the number of pins in a GPIO bank
as it depends on the SoC variant.

Change-Id: I4481774152b3c6bf35bf986f58e357c2f9c19176
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Relation between GPIO banks and their base address and offset address
if platform dependent. This change moves helper functions
stm32_get_gpio_bank_base() and stm32_get_gpio_bank_offset() from
plat/st/common to plat/st/stm32mp1/.

Change-Id: Id3d03e585746aa5509c6fab7d88183a92d561e3f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

This patch validates that PSTATE_STANDBY is set as the C6 power state type.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846ab61c007eeba3c180e5aa

Tegra194 platforms removed support to power down CPUs during CPU suspend. This
patch removes the support for CPU suspend power down as a result.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifde72c90c194582a79fb80904154b9886413f16e

The arm_fpga port requires a DTB, to launch a BL33 payload.
To make this port more flexible, we can also use the information in the
DT to configure the console driver.
For a start, find the DT node pointed to by the stdout-path property, and
read the base address from there.
This assumes for now that the stdout-path points to a PL011 UART.

This allows to remove platform specific addresses from the image. We
keep the original base address for the crash console.

Change-Id: I46a990de2315f81cae4d7913ae99a07b0bec5cb1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Now that we have an implementation for getting the node offset of the
stdout-path property in the generic fdt_wrappers code, use that to
replace the current ST platform specific implementation.

Change-Id: I5dd05684e7ca3cb563b5f71c885e1066393e057e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Since we use a DTB with all platform information to pass this on to a
kernel loaded as BL33, we can as well make use of it for our own
purposes.

Every DT would contain a node for the GIC(v3) interrupt controller, so
we can read the base address for the distributor and redistributors from
there.

This avoids hard coding this information in the code and allows for a more
flexible binary.

Change-Id: Ic530e223a21a45bc30a07a21048116d5af69e972
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The stdout-path property in the /chosen node of a DTB points to a device
node, which is used for boot console output.
On most (if not all) ARM based platforms this is the debug UART.
The ST platform code contains a function to parse this property and
chase down eventual aliases to learn the node offset of this UART node.

Introduce a slightly more generalised version of this ST platform function
in the generic fdt_wrappers code. This will be useful for other platforms
as well.

Change-Id: Ie6da47ace7833861b5e35fe8cba49835db3659a5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The ARM Generic Timer DT binding describes an (optional) property to
declare the counter frequency. Its usage is normally discouraged, as the
value should be read from the CNTFRQ_EL0 system register.

However in our case we can use it to program this register in the first
place, which avoids us to hard code a counter frequency into the code.
We keep some default value in, if the DT lacks that property for
whatever reason.

Change-Id: I5b71176db413f904f21eb16f3302fbb799cb0305
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The STM32 platform port parse DT nodes to find base address to
peripherals. It does this by using its own implementation, even though
this functionality is generic and actually widely useful outside of the
STM32 code.

Re-implement fdt_get_reg_props_by_name() on top of the newly introduced
fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c.
This is removes the assumption that #address-cells and #size-cells are
always one.

Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

The SCP firmware on the ARM FPGA initialises the UART already. This allows
us to treat the PL011 as an SBSA Generic UART, which does not require
any further setup.

This in particular removes the need for any baudrate and base clock related
settings to be hard coded into the BL31 image.

Change-Id: I16fc943526267356b97166a7068459e06ff77f0f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

At the moment the fconf_populate_gicv3_config() implementation is
somewhat incomplete: First it actually fails to store the retrieved
information (the local addr[] array is going nowhere), but also it makes
quite some assumptions about the device tree passed to it: it needs to
use two address-cells and two size-cells, and also requires all five
register regions to be specified, where actually only the first two
are mandatory according to the binding (and needed by our code).

Fix this by introducing a proper generic function to retrieve "reg"
property information from a DT node:
We retrieve the #address-cells and #size-cells properties from the
parent node, then use those to extract the right values from the "reg"
property. The function takes an index to select one region of a reg
property.

This is loosely based on the STM32 implementation using "reg-names",
which we will subsume in a follow-up patch.

Change-Id: Ia59bfdf80aea4e36876c7b6ed4d153e303f482e8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Dynamic configuration properties are fconf properties. Modify the
compatible string from "arm,.." to "fconf,.." to reflect this.
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: I85eb75cf877c5f4d3feea3936d4c348ca843bc6c