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Now that we have split the native and the SCPI version of the PSCI ops,
we can introduce build options to compile in either or both of them.

If one version is not compiled in, some stub functions make sure the
common code still compiles and makes the right decisions.

By default both version are enabled (as before), but one of them can be
disabled on the make command line, or via a platform specific Makefile.

Change-Id: I0c019d8700c0208365eacf57809fb8bc608eb9c0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>

In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out to be
a good decision, as some newer SoCs omit the ARISC, and thus cannot run
SCP firmware.

However, keeping the two implementations in one file makes things
unnecessarily messy. First, it is difficult to compile out the
SCPI-based implementation where it is not applicable. Second the check
is done in each callback, while scpi_available is only updated at boot.
This makes the individual callbacks unnecessarily complicated.

It is cleaner to provide two entirely separate implementations in two
separate files. The native implementation does not support any kind of
CPU suspend, so its callbacks are greatly simplified. One function,
sunxi_validate_ns_entrypoint, is shared between the two implementations.

Finally, the logic for choosing between implementations is kept in a
third file, to provide for platforms where only one implementation is
applicable and the other is compiled out.

Change-Id: I4914f07d8e693dbce218e0e2394bef15c42945f8
Signed-off-by: Samuel Holland <samuel@sholland.org>

- When the SCPI shutdown/reset command returns success, the SCP is
  still waiting for the CPU to enter WFI. Do that.
- Peform board-level poweroff before CPU poweroff. If there is a PMIC
  available, it will turn everything off including the CPUs, so doing
  CPU poweroff first is a waste of cycles.
- During poweroff, attempt to turn off the local CPU using the ARISC.
  This should use slightly less power than just an infinite WFI.
- Drop the WFI in the reset failure path. The panic will hang anyway.

Change-Id: I897efecb3fe4e77a56041b97dd273156ec51ef8e
Signed-off-by: Samuel Holland <samuel@sholland.org>

When operating on the local cpu, sunxi_cpu_power_off_self() only "arms"
the ARISC to perform the power-off process; the SCP waits for the CPU to
enter WFI before acutally powering it off. Since this matches the
expected split between .pwr_domain_off and .pwr_domain_pwr_down_wfi, we
can move the sunxi_cpu_power_off_self() call to sunxi_pwr_domain_off().
Since that change makes sunxi_pwr_down_wfi() equivalent to the default
implementation, the callback is no longer needed.

Change-Id: I7d65f66c550d1c69fa5e9945affd7a25b3d3ef42
Signed-off-by: Samuel Holland <samuel@sholland.org>

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.
This actually simplifies things, because all callers either operate on
the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
(sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
to choose the appropriate code path.

Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
Signed-off-by: Samuel Holland <samuel@sholland.org>

Disabling secondary CPUs during boot is unnecessary because the other
CPUs are already in reset, and it saves an entirely insignificant amount
of power. Let's remove this bit of code that was added mostly "because
we can", and along with it remove an unconditional dependency on the CPU
ops functions.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7

Checking the exceptional case and letting the success case fall through
is not only more idiomatic, but it also allows adding more exceptional
cases in the future, such as a check for overlapping secure DRAM.

Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d
Signed-off-by: Samuel Holland <samuel@sholland.org>

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
Signed-off-by: Samuel Holland <samuel@sholland.org>

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary contract. First, the SCPI protocol has no way to represent
HW_STANDBY at the CPU power level. Second, the SCPI implementation
maintains its own logical view of power states, and its implementation
of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
Thus it cannot provide "the physical view of power state", as required
for this function by the PSCI specification.

Since the function is optional, drop it.

Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
Signed-off-by: Samuel Holland <samuel@sholland.org>

The base address of UART peripheral should be given in R0, not in R1.
Otherwise the console_stm32_core_flush issues an assert message.
This issue was highlighted with recent changes in console flush functions.

Change-Id: Iead01986fdbbf30ad2fd9fa515a1d2b611b4e591
Signed-off-by: Yann Gautier <yann.gautier@st.com>

* changes:
  libc/snprintf: use macro to reduce duplicated code
  libc/snprintf: add support to print "%" character
  libc/printf: add support to print "%" character

To avoid a potential out-of-bounds access, check whether
a device exists on a channel before calling the corresponding
clone function.
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b

* changes:
  plat/arm/css/sgi: Fix assert expression issue
  plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue

Violation of MISRA-C Rule 14.4
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4

The issue is that, when interrupt is triggered and RAS handler
is entered, after interrupt handler finishes, TF-A will re-enter
bl32 and then crash.
sdei_dispatch_event() may return failing result in some cases,
for example kernel may not have registered a handler or RAS event
may happen early during boot. We restore the NS context when
sdei_dispatch_event() returns failing result.

error log :
Received delegated event
X0 :  0xC4000061
X1 :  0x0
X2 :  0x0
X3 :  0x0
Received event - 0xC4000061 on cpu 0
UnRecognized Event - 0xC4000061
Failed delegated event 0xC4000061, Status Invalid Parameter
Unhandled Exception in EL3.
x30            = 0x000000000401f700
x0             = 0xfffffffffffffffe
x1             = 0xfffffffffffffffe
x2             = 0x00000000600003c0
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f

* changes:
  doc: renesas: Update RZ/G2 code owner list
  plat: renesas: rzg: DT memory node enhancements
  renesas: rzg: emmc: Enable RZ/G2M support
  plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
  drivers: renesas: rzg: Add HiHope RZ/G2M board support
  tools: renesas: Add tool support for RZ/G2 platforms

* changes:
  marvell: uart: a3720: Fix macro name for 6th bit of Status Register
  marvell: uart: a3720: Implement console_a3700_core_getc

* changes:
  qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller
  qemu/qemu_sbsa: topology is different from qemu so add handling
  qemu/common : change DEVICE2 definition for MMU
  qemu/aarch64/plat_helpers.S : calculate the position shift

Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c

Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one
character to buffer, and then increase character counter by one in one
single statement, so that 4 similar code pieces can be cleaned.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1

Enable snprintf()/vsnprintf() in TF-A to print "%" character as C
standard, which may be used in platform porting to print percentage
information.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8

Enable printf() in TF-A to print "%" character as C standard, which
may be used in platform porting to print percentage information.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.

Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7

DEVICE2 is not currently used on qemu platform but is needed for
a future patch for qemu_sbsa platform. Change its definition to
RW and add it to all levels of arm-tf similar to DEVICE1 definition.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf

Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.

Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h
for both qemu and qemu_sbsa to enable this calculation.
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2

The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.

The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.

This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.

Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.

There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.

In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.

So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART_RX_REG register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708

* changes:
  doc: renesas: Update code owner for Renesas platforms
  doc: renesas: Document platforms based on RZ/G2 SoC's
  renesas: rzg: Add PFC support for RZ/G2M
  renesas: rzg: Add QoS support for RZ/G2M
  renesas: rzg: Add support for DRAM initialization

* changes:
  Use preallocated parts of the HASH struct
  Free arguments copied with strdup
  Free keys after use
  Free X509_EXTENSIONs

* changes:
  Workaround for Cortex N1 erratum 1946160
  Workaround for Cortex A78 erratum 1951500

* changes:
  plat: renesas: common: Include ulcb_cpld.h conditionally
  plat: renesas: Move to common
  plat: renesas: aarch64: Move to common
  drivers: renesas: Move ddr/qos/qos header files
  drivers: renesas: rpc: Move to common
  drivers: renesas: avs: Move to common
  drivers: renesas: auth: Move to common
  drivers: renesas: dma: Move to common
  drivers: renesas: watchdog: Move to common
  drivers: renesas: rom: Move to common
  drivers: renesas: delay: Move to common
  drivers: renesas: console: Move to common
  drivers: renesas: pwrc: Move to common
  drivers: renesas: io: Move to common
  drivers: renesas: eMMC: Move to common

* changes:
  drivers: renesas: Move plat common sources
  plat: renesas: Move headers and assembly files to common folder
  plat: renesas: rcar: include: Code cleanup
  plat: renesas:rcar: Fix checkpatch warnings
  plat: renesas: rcar: Fix checkpatch warnings
  plat: renesas:rcar: Code cleanup
  plat: renesas: rcar: Fix coding style