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  1. 07 Apr, 2018 2 commits
    • Jiafei Pan's avatar
      fix instruction address range limitation · b4ad9768
      Jiafei Pan authored 
      

For the adr instruction, it require the label's offset from the
address of this instruction must be in the range +/-1MB. If the
option "BL2_IN_XIP_MEM" is set to '1', in some cases, BL2's RW
memory will not in the range of +/-1MB from BL2's RO memory region.
so we need to use ldr instruction to cover this case.
Signed-off-by: default avatarJiafei Pan <Jiafei.Pan@nxp.com>
      b4ad9768
    • Jiafei Pan's avatar
      Add support for BL2 in XIP memory · 7d173fc5
      Jiafei Pan authored 
      

In some use-cases BL2 will be stored in eXecute In Place (XIP) memory,
like BL1. In these use-cases, it is necessary to initialize the RW sections
in RAM, while leaving the RO sections in place. This patch enable this
use-case with a new build option, BL2_IN_XIP_MEM. For now, this option
is only supported when BL2_AT_EL3 is 1.
Signed-off-by: default avatarJiafei Pan <Jiafei.Pan@nxp.com>
      7d173fc5
  3. 04 Apr, 2018 1 commit
  5. 03 Apr, 2018 2 commits
  7. 31 Mar, 2018 1 commit
    • Michalis Pappas's avatar
      qemu: don't use C functions for the crash console callbacks · 0e24ea81
      Michalis Pappas authored 
      

Use the console_pl011_core_* functions directly in the crash console
callbacks.

This bypasses the MULTI_CONSOLE_API for the crash console (UART1), but
allows using the crash console before the C runtime has been initialized
(eg to call ASM_ASSERT). This retains backwards compatibility with respect
to functionality when the old API is used.

Use the MULTI_CONSOLE_API to register UART0 as the boot and runtime
console.

Fixes ARM-software/tf-issues#572
Signed-off-by: default avatarMichalis Pappas <mpappas@fastmail.fm>
      0e24ea81
  9. 29 Mar, 2018 8 commits
  11. 28 Mar, 2018 2 commits
  13. 27 Mar, 2018 3 commits
    • Jonathan Wright's avatar
      psci: initialize array fully to comply with MISRA · 2271cb05
      Jonathan Wright authored 
      

Initializes each element of the last_cpu_in_non_cpu_pd array in PSCI
stat implementation to -1, the reset value. This satisfies MISRA rule
9.3.

Previously, only the first element of the array was initialized to -1.

Change-Id: I666c71e6c073710c67c6d24c07a219b1feb5b773
Signed-off-by: default avatarJonathan Wright <jonathan.wright@arm.com>
      2271cb05
    • Joel Hutton's avatar
      Clean usage of void pointers to access symbols · 9f85f9e3
      Joel Hutton authored 
      

Void pointers have been used to access linker symbols, by declaring an
extern pointer, then taking the address of it. This limits symbols
values to aligned pointer values. To remove this restriction an
IMPORT_SYM macro has been introduced, which declares it as a char
pointer and casts it to the required type.

Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0
Signed-off-by: default avatarJoel Hutton <Joel.Hutton@Arm.com>
      9f85f9e3
    • Antonio Nino Diaz's avatar
      rpi3: Use new console APIs · e0f21f62
      Antonio Nino Diaz authored 
      

Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.

The crash console doesn't use this API, it uses internally the core
functions of the 16550 console.

`bl31_plat_runtime_setup` is no longer needed. When this platform port
was introduced, that function used to disable the console. It was needed
to override that behaviour. The new behaviour is to switch to the
runtime console. The console is registered for all scopes (boot, crash
and runtime) in `rpi3_console_init` so it is not needed to override the
default behaviour anymore.

Update documentation.

Change-Id: If2ee8f91044216183b7ef142e5c05ad6220ae92f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      e0f21f62
  15. 26 Mar, 2018 8 commits
  17. 25 Mar, 2018 1 commit
  19. 24 Mar, 2018 1 commit
  21. 23 Mar, 2018 1 commit
  23. 22 Mar, 2018 7 commits
  25. 21 Mar, 2018 3 commits