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  1. 21 Jun, 2018 17 commits
  3. 20 Jun, 2018 1 commit
    • Soby Mathew's avatar
      ARM Platforms: Update CNTFRQ register in CNTCTLBase frame · 342d6220
      Soby Mathew authored 
      

Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase
frame of the system timer. ARM ARM states that "The instance of
the register in the CNTCTLBase frame must be programmed with this
value as part of system initialization."

The psci_arch_setup() updates the CNTFRQ system register but
according to the ARM ARM, this instance of the register is
independent of the memory mapped instance. This is only an issue
for Normal world software which relies on the memory mapped
instance rather than the system register one.

This patch resolves the issue for ARM platforms.

The patch also solves a related issue on Juno, wherein
CNTBaseN.CNTFRQ can be written and does not reflect the value of
the register in CNTCTLBase frame. Hence this patch additionally
updates CNTFRQ register in the Non Secure frame of the CNTBaseN.

Fixes ARM-Software/tf-issues#593

Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      342d6220
  5. 19 Jun, 2018 17 commits
  7. 15 Jun, 2018 5 commits
    • John Tsichritzis's avatar
      Panic in BL1 when TB_FW_CONFIG is invalid · 355e0967
      John Tsichritzis authored 
      

In Arm platforms, when using dynamic configuration, the necessary
parameters are made available as a DTB. The DTB is loaded by BL1 and,
later on, is parsed by BL1, BL2 or even both, depending on when
information from the DTB is needed.

When the DTB is going to be parsed, it must be validated first, to
ensure that it is properly structured. If an invalid DTB is detected
then:
  - BL1 prints a diagnostic but allows execution to continue,
  - BL2 prints a diagnostic and panics.

Now the behaviour of BL1 is changed so for it also to panic. Thus, the
behaviour of BL1 and BL2 is now similar.

Keep in mind that if BL1 only loads the DTB but it doesn't need to
read/write it, then it doesn't validate it. The validation is done only
when the DTB is actually going to be accessed.

Change-Id: Idcae6092e6dbeab7248dd5e041d6cbb7784fe410
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      355e0967
    • Andre Przywara's avatar
      allwinner: Add security setup · acb8b3ca
      Andre Przywara authored 
      

Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure world.
This affects some clocks, DMA channels and the Secure Peripheral
Controller (SPC). The latter controls access to most devices, but is not
active unless booting with the secure boot fuse burnt.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      acb8b3ca
    • Samuel Holland's avatar
      allwinner: Add platform PSCI functions required for SMP · 560581ec
      Samuel Holland authored 
      

The reset vector entry point is preserved across CPU resets, so it only
needs to be set once at boot.

Hotplugged CPUs are not actually powered down, but are put in a wfi with
the GIC disconnected.

With this commit, Linux is able to enable, hotplug and use all four CPUs.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      560581ec
    • Samuel Holland's avatar
      allwinner: Add functions to control CPU power/reset · 333d66cf
      Samuel Holland authored 
      

sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI directly, because it is not possible for a CPU to use this function
to power itself down. Power cannot be shut off until the outputs are
clamped, and MMIO does not work once the outputs are clamped.

But at least CPU0 can shutdown the other cores early in the BL31 boot
process and before shutting down the system.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      333d66cf
    • Samuel Holland's avatar
      allwinner: Add Allwinner A64 support · 64b3d9d8
      Samuel Holland authored 
      

The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      64b3d9d8