- 18 Jan, 2019 7 commits
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Steven Kao authored
This patch adds a hook to get the number of smmu devices and removes the NUM_SMMU_DEVICES macro. Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc41 Signed-off-by: Steven Kao <skao@nvidia.com>
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Steven Kao authored
This patch changes direct writes to ACTLR_ELx registers to use read-modify-write instead. Change-Id: I6e0eaa6974583f3035cb3724088f3f1c849da229 Signed-off-by: Steven Kao <skao@nvidia.com>
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Samuel Payne authored
This patch disables SMMU hardware before suspending the SE block, for the context save operation to complete. The NS word will re-enable SMMU when we exit System Suspend. Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d Signed-off-by: Samuel Payne <spayne@nvidia.com>
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Anthony Zhou authored
Main fixes: Add suffix U for constant [Rule 10.1] Match the operands type [Rule 10.4] Use UL replace U for that constant define that need do "~" operation [Rule 12.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Add function define to header file [Rule 8.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Ifa3ba4e75046697cfede885096bee9a30efe6519 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
Main fixes: Add parentheses to avoid implicit operator precedence [Rule 12.1] Fixed if statement conditional to be essentially boolean [Rule 14.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Bug 200272157 Change-Id: Ic3ab5a3de95aeb6d2265df940f7fb35ea0f19ab0 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch adds the driver for the general purpose DMA hardware block on newer Tegra SoCs. The GPCDMA is a special purpose DMA used to speed up memory copy operations to/from DRAM and TZSRAM. This patch introduces a macro 'USE_GPC_DMA' to allow platforms to override CPU based memory operations. Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 16 Jan, 2019 13 commits
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Harvey Hsieh authored
This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as they have already been fixed in the hardware. To allow the .S file to include macros, add proper guards to tegra_platform.h. Change-Id: I0826d3c54faeffc9cb0709331f47cbdf25d4b653 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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Krishna Reddy authored
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO) based on the latest info received from HW team as a part of BW issues debug. SMMU Client config register are obsolete from T186. Clean up the unnecessary register definitions and programming of these registers. Cleanup unnecessary macros as well. Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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Varun Wadekar authored
This patch memmaps all the IRAM memory banks during boot. The BPMP firmware might place the channels in any of the IRAMs, so it is better to map all the banks to avoid surprises. Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch sets up the clock for the UART console, for real Silicon and FPGA platforms. FPGA platforms run the UART clock source at 13MHz, whereas the clock cource runs at 408MHz for real silicon. Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds helper functions to find out the chip ID of the Tegra SoC. Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds support for simulation platforms as well as fixes issues flagged by the MISRA scans. Main MISRA fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix return type doesn't match the function type [Rule 10.3] * Use single return point instead of multiple [Rule 15.5] * Change return type for the tegra_platform_is_x handlers to bool Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 18 Dec, 2018 1 commit
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Varun Wadekar authored
This patch converts Tegra platforms to support native GICv2 drivers. This involves removes Tegra's GIC driver port platforms to use interrupt_props Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to bl31_early_platform_setup2(). - Remove references to removed build options. - Replace zeromem16() by zeromem(). - Use private definition of bl31_params_t. This is an incomplete migration, the platform doesn't currently compile. Change-Id: I67fbf2206678be80c3a16692024221a131cec42f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 17 Feb, 2018 1 commit
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Andreas Färber authored
Commit fdb1964c ("xlat: Introduce MAP_REGION2() macro") added a granularity field to mmap_region_t. Tegra platforms were using the v2 xlat_tables implementation in common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c where arrays are being defined. This caused the next physical address to be read as granularity, causing EINVAL error and triggering an assert. Consistently use xlat_tables_v2.h header to avoid this. Fixes ARM-software/tf-issues#548. Signed-off-by: Andreas Färber <afaerber@suse.de>
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- 15 Jun, 2017 5 commits
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Anthony Zhou authored
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Fixed assert/if statements conditions to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Convert macros form headers to unsigned ints Change-Id: I8051cc16499cece2039c9751bd347645f40f0901 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Fixed if/while statement conditional to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if/for/while statements in order to make them compound [Rule 15.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Change-Id: Ic72b248aeede6cf18bf85051188ea7b8fd8ae829 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch moves the GPU reset state check, during VideoMem resize, to the common SiP handler, to reduce code duplication. Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds explicit casts (U(x)) to integers in the tegra_def.h headers, to make them compatible with whatever operation they're used in [MISRA-C Rule 10.1] Change-Id: Ic5fc611aad986a2c6e6e6f625e0753ab9b69eb02 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 12 May, 2017 1 commit
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Sandrine Bailleux authored
For SoCs T132 and T210, the header file 'platform_def.h' used to include 'tegra_def.h' and vice versa. This patch breaks this circular dependency by making 'tegra_def.h' independent. Change-Id: I45a00a84e6ab8b93d5e9242a9ff65f03e9102a96 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 01 May, 2017 2 commits
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Varun Wadekar authored
The video memory carveout has to be re-sized depending on the Video content. This requires the NS world to send us new base/size values. Before setting up the new region, we must zero out the previous memory region, so that the video frames are not leaked to the outside world. This patch adds the logic to zero out the previous memory carveout region. Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Steven Kao authored
This patch adds the Tegra micro-seconds controller to the memory map. This allows us to use the delay_timer functionality. Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 13 Apr, 2017 5 commits
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Anthony Zhou authored
Not having U or ULL as a suffix for these enums causes a lot of unnecessary MISRA issues. This patch adds U or ULL suffix to these common enums to reduce number of MISRA issues. Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Vignesh Radhakrishnan authored
This patch adds support for fake system suspend (SC7). This is a debug mode, to ensure that a different code path is executed for cases like pre-silicon development, where a full-fledged SC7 is not possible in early stages. This particular patch ensures that, if fake system suspend is enabled (denoted by tegra_fake_system_suspend variable having a non-zero value), instead of calling WFI, a request for a warm reset is made for starting the SC7 exit procedure. This ensures that the code path of kernel->ATF and back to kernel is executed without depending on other components involved in SC7 code path. Additionally, this patch also adds support for SMC call from kernel, enabling fake system suspend mode. Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
During boot, USB3 and flash media (SDMMC/SATA) devices need access to IRAM. Because these clients connect to the MC and do not have a direct path to the IRAM, the MC implements AHB redirection during boot to allow path to IRAM. In this mode, accesses to a programmed memory address aperture are directed to the AHB bus, allowing access to the IRAM. The AHB aperture is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are initialized to disable this aperture. Once bootup is complete, we must program IRAM base/top, thus disabling access to IRAM. This patch provides functionality to disable this access. The tegra port calls this new function before jumping to the non-secure world during cold boot. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to read the chip id and identify if the current platform is Tegra186. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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