1. 13 Jul, 2021 1 commit
    • Yann Gautier's avatar
      refactor(plat/st): map DDR secure at boot · c1ad41fb
      Yann Gautier authored
      
      
      In BL2, the DDR can be mapped as secured in MMU, as no other SW
      has access to it during its execution.
      The TZC400 configuration is also updated to reflect this. When using
      OP-TEE, the TZC400 is reconfigured at the end of BL2, to match OP-TEE
      mapping. Else, SP_min will be in charge to reconfigure TZC400 to set
      DDR non-secure.
      
      Change-Id: Ic5ec614b218f733796feeab1cdc425d28cc7c103
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      c1ad41fb
  2. 27 May, 2021 1 commit
  3. 13 Oct, 2020 1 commit
  4. 11 May, 2020 1 commit
  5. 26 Mar, 2020 1 commit
    • Yann Gautier's avatar
      stm32mp1: dynamically map DDR later and non-cacheable during its test · 84686ba3
      Yann Gautier authored
      
      
      A speculative accesses to DDR could be done whereas it was not reachable
      and could lead to bus stall.
      To correct this the dynamic mapping in MMU is used.
      A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
      once DDR access is setup. It is then unmapped and a new mapping DDR is done
      with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
      load.
      
      The disabling of cache during DDR tests is also removed, as now useless.
      A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
      instead.
      
      PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.
      
      BL33 max size is also updated to take into account the secure and shared
      memory areas. Those are used in OP-TEE case.
      
      Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      84686ba3
  6. 02 Sep, 2019 2 commits
  7. 17 Jun, 2019 1 commit
  8. 14 Feb, 2019 4 commits