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  1. 04 Jun, 2021 1 commit
    • Yann Gautier's avatar
      refactor(plat/st): avoid fixed DT address · c20b0606
      Yann Gautier authored 
      

Device Tree address is now a parameter for dt_open_and_check() function.
This will allow better flexibility when introducing PIE and FIP.
The fdt pointer is now only assigned if the given address holds
a valid device tree file. This allows removing the fdt_checked variable,
as we now check fdt is not null.

Change-Id: I04cbb2fc05c9c711ae1c77d56368dbeb6dd4b01a
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      c20b0606
  3. 03 Jun, 2021 5 commits
  5. 02 Jun, 2021 1 commit
  7. 01 Jun, 2021 3 commits
  9. 31 May, 2021 1 commit
  11. 28 May, 2021 2 commits
    • johpow01's avatar
      fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs · c6ac4df6
      johpow01 authored 
      

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195
      c6ac4df6
    • Pali Rohár's avatar
      fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation · 66a77528
      Pali Rohár authored 
      

UART parent clock is by default the platform's xtal clock, which is
25 MHz.

The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
  Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.

Change the code for divisor calculation to
  Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to 25 MHz.

The final UART divisor for default baudrate 115200 is not affected by
this change.

(Note that the parent clock rate should not be defined via a macro,
since the xtal clock can also be 40 MHz. This is outside of the scope of
this fix, though.)
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
      66a77528
  13. 27 May, 2021 2 commits
  15. 26 May, 2021 3 commits
  17. 25 May, 2021 3 commits
  19. 21 May, 2021 1 commit
    • Igor Opaniuk's avatar
      feat(plat/imx8m): add SiP call for secondary boot · 9ce232fe
      Igor Opaniuk authored 
      In iMX8MM it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case the bootloader image is faulty OR can be
enforced by the user. To trigger that switch the
PERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register.
As the bit is retained after WARM reset, that permits to control
BootROM behavior regarding what boot image it will boot after
reset: primary or secondary.

This is useful for reliable bootloader A/B updates, as it permits
switching between two copies of bootloader at different offsets of
the same storage.

If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address
0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1,
the boot ROM reads that secondary image table from address 0x8200
on the boot media and uses the address specified in the table for
the secondary image.

Secondary Image Table contains the sector of secondary bootloader
image, exluding the offset to that image (explained below in the
note). To generate the Secondary Image Table, use e.g.:
$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11'
         '\x00\x00\x10\x0\x0\x00\x0\x0\x0'
  > /tmp/sit.bin
$ hexdump  -vC /tmp/sit.bin
  00000000  00 00 00 00
  00000004  00 00 00 00
  00000008  33 22 11 00 <--- This is the "tag"
  0000000c  00 10 00 00 <--- This is the "firstSectorNumber"
  00000010  00 00 00 00

You can also use NXP script from [1][2] imx-mkimage tool for
SIT generation. Note that the firstSectorNumber is NOT the offset
of the IVT, but an offset of the IVT decremented by Image Vector
Table offset (Table 6-25. Image Vector Table Offset and Initial
Load Region Size for iMX8MM/MQ), so for secondary SPL copy at
offset 0x1042 sectors, firstSectorNumber must be 0x1000
(0x42 sectors * 512 = 0x8400 bytes offset).

In order to test redundant boot board should be closed and
SD/MMC manufacture mode disabled, as secondary boot is not
supported in the SD/MMC manufacture mode, which can be disabled
by blowing DISABLE_SDMMC_MFG (example for iMX8MM):
> fuse prog -y 2 1 0x00800000

For additional details check i.MX 8M Mini Apllication Processor
Reference Manual, 6.1.5.4.5 Redundant boot support for
expansion device chapter.

[1] https://source.codeaurora.org/external/imx/imx-mkimage/


[2] scripts/gen_sit.sh
Change-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c
Signed-off-by: default avatarIgor Opaniuk <igor.opaniuk@foundries.io>
      9ce232fe
  21. 19 May, 2021 1 commit
    • Manish V Badarkhe's avatar
      feat(hw_crc): add support for HW computed CRC · a1cedadf
      Manish V Badarkhe authored 
      

Added support for HW computed CRC using Arm ACLE intrinsics.
These are built-in intrinsics available for ARMv8.1-A, and
onwards.
These intrinsics are enabled via '-march=armv8-a+crc' compile
switch for ARMv8-A (supports CRC instructions optionally).

HW CRC support is enabled unconditionally in BL2 for all Arm
platforms.

HW CRC calculation is verified offline to ensure a similar
result as its respective ZLib utility function.

HW CRC calculation support will be used in the upcoming
firmware update patches.

Change-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      a1cedadf
  23. 17 May, 2021 1 commit
  25. 10 May, 2021 1 commit
  27. 03 May, 2021 1 commit
    • Pranav Madhu's avatar
      feat(plat/sgi): enable AMU for RD-V1-MC · e8b119e0
      Pranav Madhu authored 
      

AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).

Change-Id: I33be594cee669e7f4031e5e5a371eec7c7451030
Signed-off-by: default avatarPranav Madhu <pranav.madhu@arm.com>
      e8b119e0
  29. 30 Apr, 2021 2 commits
  31. 29 Apr, 2021 2 commits
  33. 28 Apr, 2021 2 commits
    • David Horstmann's avatar
      refactor(plat/arm): store UUID as a string, rather than ints · 7d111d99
      David Horstmann authored 
      

NOTE: Breaking change to the way UUIDs are stored in the DT

Currently, UUIDs are stored in the device tree as
sequences of 4 integers. There is a mismatch in endianness
between the way UUIDs are represented in memory and the way
they are parsed from the device tree. As a result, we must either
store the UUIDs in little-endian format in the DT (which means
that they do not match up with their string representations)
or perform endianness conversion after parsing them.

Currently, TF-A chooses the second option, with unwieldy
endianness-conversion taking place after reading a UUID.

To fix this problem, and to make it convenient to copy and
paste UUIDs from other tools, change to store UUIDs in string
format, using a new wrapper function to parse them from the
device tree.

Change-Id: I38bd63c907be14e412f03ef0aab9dcabfba0eaa0
Signed-off-by: default avatarDavid Horstmann <david.horstmann@arm.com>
      7d111d99
    • Manish V Badarkhe's avatar
      refactor(plat/arm): replace FIP base and size macro with a generic name · 49e9ac28
      Manish V Badarkhe authored 
      

Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a
generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE
so that these macros can be reused in the subsequent GPT based support
changes.

Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      49e9ac28
  35. 27 Apr, 2021 3 commits
    • Pali Rohár's avatar
      plat: marvell: armada: a3k: Add new compile option A3720_DB_PM_WAKEUP_SRC · f2800a47
      Pali Rohár authored 
      

This new compile option is only for Armada 3720 Development Board. When
it is set to 1 then TF-A will setup PM wake up src configuration.

By default this new option is disabled as it is board specific and no
other A37xx board has PM wake up src configuration.

Currently neither upstream U-Boot nor upstream Linux kernel has wakeup
support for A37xx platforms, so having it disabled does not cause any
issue.

Prior this commit PM wake up src configuration specific for Armada 3720
Development Board was enabled for every A37xx board. After this change it
is enabled only when compiling with build flag A3720_DB_PM_WAKEUP_SRC=1
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I09fea1172c532df639acb3bb009cfde32d3c5766
      f2800a47
    • Aditya Angadi's avatar
      feat(board/rdn2): add support for variant 1 of rd-n2 platform · fe5d5bbf
      Aditya Angadi authored 
      

Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a
variant of RD-N2 platform with a reduced interconnect mesh size (3x3)
and core count (8-cores). Its platform variant id is 1.

Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      fe5d5bbf
    • Aditya Angadi's avatar
      feat(plat/sgi): introduce platform variant build option · cfe1506e
      Aditya Angadi authored 
      

A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.

An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1

Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      cfe1506e
  37. 26 Apr, 2021 1 commit
  39. 23 Apr, 2021 4 commits